What are the errors that can be calibrated in an ADC?

Hello,
I am starter in ADC design. While I am going through ADC specifications, i found that ENOB =12 though it is 16 bit ADC. Then what is the specific reason for using 16 bit ADC than 12 bit ADC? Can not we use an 12-bit ADC without any missing codes?

For any ADC, what are the parameters that can be calibrated in the design like DNL, INL etc?

Please help me on this.

Enob is ( signal+noise + 1.76)/6.02
1.76 is the ideal quantization noise
6.02 is the quantum per bit

So while you may have 16 bits you care about the number of bits (dBs) from the noise floor to a full scale signal. This is the useable dynamic range. Depending on the sample rate there are 16 bit ADCs with much higher than a ENOB of only 12 bits.

With narrow band filtering after the ADC you can reduce the noise and have system performance better than the ENOB specified for the device in some situations.

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INL and DNL are intrinsic to the ADC and can not be directly calibrated out.

Parameters that can be readily calibrated would be any gain and offset error.

crutschow said:

Parameters that can be readily calibrated would be any gain and offset error.

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Thanks for your reply!

As you said, we will not have any control over DNL, INL, THD, ENOB which are inherent to ADC. We can only calibrate only few of the static parameters like Gain error and offset error.


In my application, i have to monitor an input analog signal with 100Hz useful frequency. 10 bits is enough from resolution point of view. How to start selecting ADC, I mean what are the main parameters that I need look into to start the design.

Hi HMS1021,

Even with Narrow band filtering, still we can have spurs well within the bandwidth which will still disturb ENOB.Please correct me if I'm wrong.

yuvan said:

Hi HMS1021,

Even with Narrow band filtering, still we can have spurs well within the bandwidth which will still disturb ENOB.Please correct me if I'm wrong.

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I understand what you are saying but ENOB has a specific meaning which is basically noise floor to full scale signal / 6.02.
SFDR has its own definition.

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How to start selecting ADC, I mean what are the main parameters that I need look into to start the design.

10 bits and 100Hz is a common ADC. I would look for the following if I was doing the design:
1 type of interface ( SPI, parallel, etc)
2 package type (SMT, BGA, through hole, etc)
3 Power consumption
4 Nyquist or Continuous Sigma-Delta ( CSD may have an advantage of an easier antialiasing filter since images may be further out of band permitting a higher filter cut off frequency and therefore smaller components)
5 Cost / availability
6 Reference voltage
7 diff or single ended input
8 input impedance and need for buffer amp
9 power supply voltages
10 SFDR

These are not in priority order but all will impact the design.