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speed of operation of filter

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kannan2590

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In VLSI books like keshav parhi it is told that for the direct form i of fir filter the execution time is tm+(2*ta)

tm->execution time of multiplier
ta-> execution time of adder.

here i am considering an fir filter with 3 multipliers and 2 adders.

for transposed implementation it is tm+ta.

Now in the synthesis report only the maximum frequency of the entire design will be given but where is the execution time(or maximum frequency) with which the multiplier or adder operates will be given and how to check the execution time of the multiplier and adder in the synthesis report?Can anybody tell me?The synthesis tool used by me is xilinx
 

The speed has depend on clock rate and how much delay of each part of circuit , one that control maximum frequency .

Consult the data sheet of each chip !!!!!!!!!!!!!!!!!
To find propagation delay of your circuit, and then calculate Fmax .
 

For an FPGA, a small filter (eg, 3 taps) can be made to run at any clock rate supported by the FPGA as long as the latency is long enough.
 

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