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May calibre run LVS check in mixed-signal design?

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harryzhu

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In mixed-signal design, there's schematic in analog part, and verilog netlist in digital part, may calibre run LVS check based on this condition? How can I do it? Thanks for your help!
 

Calibre has a tool to change verilog to spice. But you need the spice netlist for each standard cell definition.
 

I run v2lvs to convert verilog to cdl netlist by using as this:

v2lvs -lsp stdcell.v -lsp *v -o output.cdl -s0 gnd -s1 vdd -v top_verilog.v

But I met another question, since I define the bus such as cir[0-31], and which is not recognized, how can I resolve it?

I know there's another way to run LVS using dracula in mixed-signal design, but I don't know the detailed flow.
 

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