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Each ROM Data to be stored in separate registers

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maysri

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Hi,

In ROM, I'm storing 10 data and trying to pass each data to the separate register. Each register should contain each ROM data. Address of the ROM is being controlled through counter.

Code Snippet :

Code: 
-------------------------------------------------------------------------------------------
Trying to store ROM data 's_data' into 'reg_data' (an array)
-------------------------------------------------------------------------------------------

--generate_data_out : for i in 0 to 9 generate
process(clk)
begin	
	if(clk'event and clk = '1') then
		for i in 0 to 9 loop
			reg_data(i) <= s_data;
		end loop;
	end if;
end process;
--end generate generate_data_out;

-------------------------------------------------------------------------------------------
Storing reg_data(0) into register
-------------------------------------------------------------------------------------------

reg_val1	: reg
				generic map (
					width		=> 16
				)
				port map (
					clk		=> clk,
					rst		=> rst,
					ce		=> ce,
					d		=> reg_data (0),
					q		=> a0
				);

-------------------------------------------------------------------------------------------------------

But in 'a0' port, full ROM data is coming inspite of storing a single data.

Kindly comment on this...

Mayank
 
Last edited by a moderator:

Code: 
entity app is
	port (
		clk		: in std_logic;
		rst		: in std_logic;
		ce		: in std_logic;
		
		a0		: out std_logic_vector(15 downto 0);
		a1		: out std_logic_vector(15 downto 0)
	);
end app;

architecture Behavioral of app is

component counter is
	generic ( width	: integer	:= 10;
		     limit	: integer	:= 512
	);
	port(clk, clr, ce : in std_logic;
		q : out std_logic_vector((width-1) downto 0);
		q_valid	: out std_logic);
end component;

component rom_file is
	generic (
		width			: integer		:= 10;
		limit			: integer		:= 512;
		FileName		: string		:= ""
	);
	port ( 
		clka			: in		std_logic; 
		ena			: in		std_logic;
		addra			: in		std_logic_vector((width-1) downto 0); 
		doa			: out		std_logic_vector(15 downto 0)
	); 
end component rom_file; 

component reg is
	generic (
		Width	      : integer		:= 16 
	);
	port (
		clk			: in		std_logic;
		ce			: in		std_logic;
		rst			: in		std_logic;
		
		d			: in		std_logic_vector((Width-1) downto 0);
		q			: out		std_logic_vector((Width-1) downto 0)
	);
end component reg;

signal s_addr		: std_logic_vector(3 downto 0);
signal s_data		: std_logic_vector(15 downto 0);

type reg_array is array (0 to 9) of std_logic_vector(15 downto 0);
signal reg_data	: reg_array;

begin

cntr1	:	counter
				generic map (
					width		=> 4,
					limit		=> 10
				)
				port map (
					clk		=> clk,
					clr		=> rst,
					ce		=> ce,
					q		=> s_addr,
					q_valid	=> open
				);
				
rom_fir	: 	rom_file
					generic map (
						width		=> 4,
						limit		=> 10,
						FileName	=> "./rom/fir_p.dat"
					)
					port map (
						clka		=> clk,
						ena		=> '1',
						addra		=> s_addr,
						doa		=> s_data
					);
					
--generate_data_out : for i in 0 to 9 generate
process(clk)
begin	
	if(clk'event and clk = '1') then
		for i in 0 to 9 loop
			reg_data(i) <= s_data;
		end loop;
	end if;
end process;
--end generate generate_data_out;

reg_val1	: reg
				generic map (
					width		=> 16
				)
				port map (
					clk		=> clk,
					rst		=> rst,
					ce		=> ce,
					d		=> reg_data (0),
					q		=> a0
				);
				
reg_val2	: reg
				generic map (
					width		=> 16
				)
				port map (
					clk		=> clk,
					rst		=> rst,
					ce		=> ce,
					d		=> reg_data (1),
					q		=> a1
				);
end Behavioral;

For counter and ROM, I'm using the XILINX HDL codes. In entity app, I've reduced the output port from 10 to 2 (for simplicity)
Click to expand...
TrickyDicky said:
I suggest you post the whole code.
Click to expand...
 

all I see is 10 registers storing the same value.
I dont understand what you think the problem is. You have to remember that loops in VHDL unroll into parrallel logic.
 

My main objective is to store each value of ROM into separate registers. Suppose ROM contains {0AD4, 0087, AF41,....}, now reg 1 should contain 0AD4 only, reg 2 0087 only... For this I wrote the above code but it's not working...Kindly guide me
 

Maysri,

Tricky gave you the answer, but perhaps you have a SW background?

What Tricky means is the equivalent code to your loop is:
Code VHDL - [expand]
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process(clk)
begin
 if (clk'event and clk = '1') then
    reg_data(0) <= s_data;
    reg_data(1) <= s_data;
    reg_data(2) <= s_data;
    reg_data(3) <= s_data;
    reg_data(4) <= s_data;
    reg_data(5) <= s_data;
    reg_data(6) <= s_data;
    reg_data(7) <= s_data;
    reg_data(8) <= s_data;
    reg_data(9) <= s_data;
 end if;
end process;


To do what you desire you will need to demultiplex the s_data using a delayed version of the s_addr as the index to reg_data.

Regards,
-alan
 
Last edited:

Yes, I'm new to this field... Now it's working. Thanks for the guidance.

Thanks,

Mayank
 

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