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how to set counter start counting from 0 instead of 1?

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naught

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i`m writing a state machine and have some problems.
I tried use a 3-bit counter to control the state machine and I want the project to start its work at "cnt =0", instead of "cnt = 1".
But after the "rst" disabled, the cnt simply jumps to "1", and i intend it to start at "0".
maybe i could set the value "cnt =111" when rst = '1', then i`ll get cnt="000" when the 1st clk rising eldge comes after the rst disabled.
could anyone help provide some other ways to make the cnt = 0 at the 1st clk uprising eldge after the rst disabled?

or did write the state machine in a wrong way? i try to set the system start at a certain state, say state0, then flows to state1, state2, then repeat. now it seems
it starts at state1, then state2, then state0, then repeat....anyway, plz help... the HDL is so different from software i wrote before and really puzzling.

thanks in advance.

Code VHDL - [expand]
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process(rst,clk)
    begin
        if(rst = '1') then
            cnt <= "000";
        elsif(clk'event and clk = '1') then
            cnt <= cnt + 1;
        end if;
    end process;
 
    process(cnt)
    begin
        case cnt is
            when "000" => data_tmp <= "001";
            when "001" => data_tmp <= "010";
            when "010" => data_tmp <= "011";
            when "011" => data_tmp <= "100";
            when "100" => data_tmp <= "101";
            when "101" => data_tmp <= "110";
            when "110" => data_tmp <= "111";
            when "111" => data_tmp <= "000";
            when others => NULL;
        end case;
    end process;
 
Last edited by a moderator:

Im not sure what the problem is. When the reset is de-asserted, cnt will be at "000" until you get a rising edge of the clock, but data_tmp will be "001". In your testbench, have you aligned the clock and reset in some way? maybe you want to separate them by half a clock?
 

TrickyDicky, thanks for your reply.
I deliberately set data_tmp 1 bit larger than cnt, for better contrast, but that`s irrelevant...

when the reset is de-asserted, cnt will be at "000" until the 1st edge of the clock, then when 1st edge comes, the cnt changes to "001", and this causes "case" to start at 2nd line "when "001" => data_tmp <= "010"; "
this is what bothers me. At the 1st clock edge after reset is de-asserted, I want the cnt =000, and "case" to start work from the 1st line, " when "000" => data_tmp <= "001"; ".
it seems to me the only way to do that is to set the cnt=111 when reset is asserted.

i feel somethings wrong here, but i don`t know where...
 
Last edited:

theres nothing wrong. I suggest thinking about drawing the circuit on a peice of paper to better understand it. If you really want an asynchronous decode, then yes, you will probably have to reset cnt to "111", but you could also think about putting a register on the output of the decoder.
 
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    N

    naught

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yes, a register connected to the signal "cnt" would do the job. thanks.
cnt_register <= cnt
and then the cnt still goes to 001 when 1st clk edge comes, but the cnt_register would be 000. then then case has to use cnt_register as its sensitive word.
TrickyDicky, thanks again. you really helped a lot.
 

you would be better off from a timing perspective to register the output of the cnt decoder, rather than register the counter itself.
 

A counter is technically a FSM (albeit a very simple one) but I don't really consider a counter to be a real FSM. You should do some searches on FSM and VHDL/Verilog to see how an FSM should be coded.

If you change your async reset to a synchronous reset in your original post I think the code will behave more like you expected. Also if the reset isn't synchronously deasserted on the clock then there is a possibility of different bits of the counter to come out of reset and violate the reset recovery/removal time of the register.
https://logicsense.wordpress.com/2011/05/12/recovery-and-removal-time/

Regards,
-alan
 

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