Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Sb. could show me some mixed VHDL and Verilog design code?

Status
Not open for further replies.
W

walkon

Junior Member level 1
Joined
Oct 21, 2004
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
165
Sb. could show me some mixed VHDL and Verilog design code?

moved here by davorin
What the hell it has to do with "Analog circuit design" ??? (o;
Please post in right section next time!
 

Re: Sb. could show me some mixed VHDL and Verilog design cod

If you have ModelSim on your system, you can find a mixedHDL in the example folder of ModelSim installation directory. If you don't have it, let me know to send it to you.

Regards,
KH
 

Re: Sb. could show me some mixed VHDL and Verilog design cod

Thanks for your reply,
my modelsim version is 5.3 in Solaris
when I try to vcom set.vhd, it says
it couldn't load work.std_logic_util
 

you describe one module using verilog, and another entity using vhdl. and the top level using either verilog or vhdl which refers to both the verilog module and vhdl entity. then this is a mix vhdl and verilog design.
 

there is not much difference between use verilog separately and use verilog and vhdl,except for use them in the same module
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top