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Image processing using FPGA - Altera Cyclone IV Transreceiver Development Board

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hartejpal

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Hi All,
I need to implement an image processing algorithm on an Altera Cyclone IV Transreceiver Development Board.
The broad plan is to transfer a bit map from PC to the board through the PCIe interface and onto the RAM on the board,
the image gets processed on the board and is returned to the PC after processing again as a bit map.

Need help on two issues:-
1. I am stuck at the first step to transfer the image to the board.
2. Also not getting any of my simple programs in Verilog to be stored on the flash memory on the board so that on power recycle the board configures itself from the flash. It is important since I have to have the program loaded before PCIe on the PC detects the board.

Please indicate me to the right direction, any help will be deeply appreciated.

Thanx in anticipation
 

I guess you have the Cyclone IV GX Transceiver Starter Kit?

1. You would want to implement and understand the PCIe reference design shipped with the development kit.
2. The procedure is well explained in any development kit user manual.
 
2. For the altera dev boards - its even explained on the webpage you get by connecting to the dev board with the demo design loaded.
 
Yes, I have connected to the board update portal. Need a .flash file to proceed.
I am using Quartus II. As a trial I wanted to just create a not gate, getting input from one of the push buttons and output to one LED.
It works when I program the FPGA via the onboard USB Blaster connected to the PC and programming with Quartus II 12.0

But,i would like to have this Not gate configured automatically from the flash after power cycle.

I have the .sof file, tried to convert to.pof could not succeed.

How to proceed further?

- - - Updated - - -

I guess you have the Cyclone IV GX Transceiver Starter Kit?

1. You would want to implement and understand the PCIe reference design shipped with the development

Could not make much out of the reference design.
Still trying at it.
It needs some win pcie drivers which again are very expensive to use in custom designs.
 

if you go to the update portal, there is a link that tells you how to create a flash file for uploading to the board, and which switches to set on the board to load your design (again, if you had read the manual, you'd know all this too).

There are jungo PCIe drivers you can get for free for the reference design (again, if you read the documentation, you'd know all this already).
 
Hello every one.

I guess you have the Cyclone IV GX Transceiver Starter Kit?

1. You would want to implement and understand the PCIe reference design shipped with the development kit.
2. The procedure is well explained in any development kit user manual.

I also need to ask something similar. I am using Xilinx board, have to implement Image processing algorithm, want to transfer through PCIe to computer...
I take data from ADC. I know it is like intrusion into someone else's question, but if you can please suggest something.

Bests,
Shan
 

if you go to the update portal, there is a link that tells you how to create a flash file for uploading to the board, and which switches to set on the board to load your design (again, if you had read the manual, you'd know all this too).

Sir,
Thanx a ton for guiding me.
Have got through creating a .flash file for the simple NOT gate.
configured the board and it is functioning as desired.

Moving on to figuring out the PCIe interface.
The book you suggested below is a real heavy reading, and quite expensive for me.
Trying my hand at the PCIe reference design
and an example from Xillybus.com https://xillybus.com/pcie-download

I am making a video for this procedure to program the flash memory of the Altera board to be helpful to others like me.
Will post it on YouTube.

Please keep your suggestions coming.
 

If you use SOPC builder or QSYS (in newer quartus) you should be able to place a a PCIE core that attaches to a NIOS, and you dont have to interface to it, and it uses the easier Avalon Memory mapped interface. For a PCIe core that you generate from the megawizard, you may only have access to the avalon streaming interface. With this, you need to decode the Top Level Packets yourself. But you only need the section of the book that describes all the packets. Most of the rest of the book is very technical and you dont need it to connect to the core.
 

It is said that ' Curiosity killed the Cat'.
That is exactly what happened with me today.

Was tinkering with the Quartus II/ Programmer, with the Cyclone IV GX Starter board connected, did an auto detect of the devices attached.
It came up with EP4CGX15BF14 and EPM2210.
Just out of curiosity I checked the erase box for the EPM2210 and pressed start.




Now the default configuration is gone, i.e no green LEDs on powering on the board.

Later I checked that I am still able to program the FPGA EP4CGX15BF14 with my .sof files through the embedded USB Blaster.
But, the board update portal won't show, nor the green LEDs in the default mode.

Is there a way to reprogram the EPM2210?
I guess I would need some .sof files for this.
Eagerly awaiting some help on this.


I must mention that I have two Cyclone IV GX Starter Boards.
One that has gone bad, as mentioned above.
And the other one which is working fine.

So maybe there is a way to copy the configuration from the good board to revive the other one.
 
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Yes, I have power cycled the board and put the dip switched back to default config.
I read through the User Guide for this board 'ug_civgx_trans_starter_kit.pdf' to get it to default config. It says I need c4gx15_starter_bup.sof file to be written to the board through the programmer.

But, I guess it is available only with the dev board. I am using the web edition of Quartus II 12.0 and cannot locate the path in the directories as given in the user guide ' <install dir>\kits\cycloneIVGX_4cgx15_starter\factory_recovery\c4gx15_starter_bup.sof '

googled for it, but, no luck.
 

did you download this file and install it?
**broken link removed**
 
No, will do that. And try again.
But, the proxy in my university is barring download from ftp sites.

Let me see if I can work around it.

Appreciate your help.
 

did you download this file and install it?
**broken link removed**

Yes, I downloaded it over my gprs connection, but, unfortunately it is not suitable for my board.
It does not have the file c4gx150_fpga_bup.sof
I did find 'c4gx150_fpga_bup.sof' buy that is for a different board.

Request if any one has the dev kit for Cyclone IV GX Transreceiver Starter Board installed on your PC, please mail me the file 'c4gx150_fpga_bup.sof' for the kits directory.
Need it urgently.
 

Finally, got the correct files.
Re-programmed the Max II Controller and the board is working as before.

That was quite a good learning experience and gave me better insight of the board.

The Altera support need all kinds of verification line company name, company email etc,
I as a student do not have all that readily available to me. So hope from Altera support

Thanx TrickyDicky for you help all the way upto here.
Now getting on with the PCIe part.
 

I guess you have the Cyclone IV GX Transceiver Starter Kit?

1. You would want to implement and understand the PCIe reference design shipped with the development kit.
Yes, I have the Cyclone IV GX Transceiver Starter Kit?
I downloaded the PCIe reference design, Qsys PCI Express to External Memory Reference Design Suite for Cyclone IV GX

Programmed the board using a .flash file created from the c4gx15_qsys_pcie_gen1x1_11_1.sof file.
Installed the Jungo drivers.
Then used the application altpcie_demo_Qsys_32.exe to communicate to the board. It seems to recognize the board, and displays Cyclone IV GX logo on top left.
I then invoked various actions through the button on the bottom left of the application.
1. Scan the end point configuration space registers.
2. Scan the current PCI express board settings.
3. Scan the motherboard PCI bus.
4. Run target read.
5. Run target write.
till here the things seem to move fine.
6. Run OnChipMemory DMA Test. - It says Data verify failed. DMA read timed out.
7. Run DDR DMA Test - Again , Data verify failed. DMA read timed out.

Can't figure out why the memory reads should fail.

Am not getting a clear picture of the whole process involved from the accompanying ' an456.pdf ' document.
Please suggest how should I proceed further.
 

Still no breakthrough with the Altera Reference design.
But, got my hands on a very simple and basic design example from Xillybus https://xillybus.com/pcie-download
I think this is the best design example, available on the internet for a beginner.​

It is very good to get a feel of the PCIe communications.
The example has precompiled examples for
  1. streamwrite.exe
  2. streamread.exe
  3. memwrite.exe
  4. memread.exe

Tried the examples as follows
Used streamwrite in one command prompt and streamread on another.
any thing written on the first window is received in the second.​

used memwrite to write to the FPGA memory locations.
and then verify the same using hexdump.exe (also) part of the design examples.​

There are also the c files and the complete Quartus design for the Xillybus PCIe core.
Working on understanding these codes.

Atleast now I have a working example.
Things are finally starting to move.:grin:

XillyDemo.jpg
 
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