Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

about the ripple rejection for voltage regulator

Status
Not open for further replies.
C

cetc1525

Full Member level 3
Joined
Oct 8, 2004
Messages
174
Helped
6
Reputation
12
Reaction score
2
Trophy points
1,298
Activity points
1,396
how to improve the ripple rejection of a voltage regulator?
this is a important for a voltage regulator.
use a cap. at the feedback network or reduce the erramp's current?
 

Filter both the input and output with large and small capacitors. For example, use 0.1 uf and 47 uf on the input and output of the regulator.
 

If you have a good reference voltage, the regulator should have enougth bandwith in the feed back network to cancel input ripple.

Bastos
 

Another trick is to use two regulators in a row. The first one drops the voltage to an intermediate value that the second one can still function on.
 

moderator,your suggestion is to use a pre-regulator,aren't you?
I just use a zener diode as my reference,the comman npn-pair opamp for the erramp.It's ripple rejection is only 47dB.
 

I was suggesting using two low drop out IC regulators. Another trick is to reduce the ripple into the regulators with larger capacitors before the regulators. I have on several occasions modified commercial supplies by adding more capacitors.

Another trick with home made regulators with op amps is to power up with the reference powered from the input and then power it from the output. This is done with resistor-diode networks.
 

You can try bigger output capacitor with smaller ESR resistor to improve ripple.
When you parallel two capacitors, the capacitance will increase and ESR will decrease as well.
 

you all talk about the outer of a regulator.but I want to know can I improve it from the inner of the IC?
 

The keys of good supply rejection are:

1. High bandwith
2. High gain
2. Good PSSR of the error amplifier

Generally speaking LDOs suffer from poor rejection due to the pass element wich is usually a PMOS, if you can cope with higher voltage drop, consider using an NMOS as a pass element.

Bye
 

some books say using a NMOS should use additional voltage supple?
 

To get a low drop voltage regulator using an NMOS transistor as pass element you must use a dc/dc converter (such as charge pump) in ordet to generate a gate voltage higher than the drain voltage; in this way you may achieve a very low drop vreg but generally speaking the lower is the drop, the poorer is the svr. An NMOS is naturally less affect by the supply noise (it appears as drain-gate voltage rather than source-gate voltage as in PMOS regulators) but driving it through a dc/dc converter generated voltage generate a great deal of problems.

Bye
 

What is the capacitor value you have added on chip at the regulator output?
Nomally, 200~500pF is necessary.
I don't think the AMP u used should have a large BW.
 

pls refer to IEEE paper:

'A Precise On-Chip Voltage Generator for a Gigascale
DRAM with a Negative Word-Line Scheme'

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 8, AUGUST 1999
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top