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How to handle the varied length of output signal

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systolic

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I am doing compression algorithm using VHDL. I need to output different length of codes according to different intermediate computation results. In this way, I compress the original information.

For example, if intermediate computation result is less than certain threshold, I will output 5 bits, but if it is greater than the threshold, I only need to output 3 bits.

How could I handle the definition of the output signal?
I thougth about using 2 'Z's to concatenate with 3 bits. It didn't work, turned my output to "ZX". :(

Any suggestions or hints? TIA
 

use another output port to specify the bitwidth of the signal on the output.. and modify ur next block accordingly

out [4:0] output_sig;
out [2:0] out_length; // if u have only 5 or 3 bit lengths at output .. u can just use only one bit
 

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