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Non-blockng assignment depending on blocking assignment from different always

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Hello,

in the example below, does the blocking assignment "y = a ^ b" also block the " q <= y" assignment until y is assigned?


module nbex1 (q, a, b, clk, rst_n);
output q;
input clk, rst_n;
input a, b;
reg q, y;

always @(a or b)
y = a ^ b;

always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 1'b0;
else q <= y;
endmodule


Example 23 - Combinational and sequential logic separated into two always blocks
(from Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! -- Clifford E. Cummings)

Regards,

Leon.
 

Yes. Blocking means that the LHS is assigned immediately, available for all expressions that follow it in the sequential code. In terms of hardware synthesis, the expression a ^ b is inserted in the respective places (at least for this simple case with only one blocking assignment in effect).
 

Yes. Blocking means that the LHS is assigned immediately, available for all expressions that follow it in the sequential code. In terms of hardware synthesis, the expression a ^ b is inserted in the respective places (at least for this simple case with only one blocking assignment in effect).

Is the case, even if the blocking assignment appears in another always @ block, as in the example code?


Thank you,

Leon.
 

The problems involved with blocking assignment in multiple always blocks are discussed in the excellent Cummings paper in detail. I don't think it's approriate to retell it in a few words.

Very simple, the assignments in a different always block don't necessarily follow the blocking assignment in the first block, because the execution order of concurrent statements, including complete always blocks, is undefined.
 
Thanks. Those papers are extremely good reading material.
 

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