ned_zeppelin
Newbie level 6
I have been using Icarus Verilog along with gtkwave (on various versions of Ubuntu) for a little while now, and it has been great. However, I have recently stumbled onto a problem I am unable to solve.
This is the makefile I use (simple makefile, that I pretty much found online) :
The basic use is:
make all TESTBENCH=testbench.v
I have simulated many minor design with this setup, without any problems. However when simulating my last design, which is a bit larger (containing around 20 modules) the simulation gets a bit problematic.
Initially, the simulation finished without any problems. But as the testbench passes a certain amount of clock cycles, the simulation never finishes. No error message appears, and it does not crash, it just never finishes. The last message to be printed is this:
VCD info: dumpfile dump.vcd opened for output.
I tried simulating the exact same files in Active HDL (student edition, Windows), and it worked fine. It didn't take more than a second or two either, so the runtime is not the problem it seems.
I have tried letting iVerilog run for quite some time too without any luck. I could of course just switch to Active HDL and Windows, but that would be a last resort, as I already have a good setup going in Ubuntu with IVerilog and gtkwave.
I tried using diiferent output formats, such as lx2 etc. as well but it didn't help.
Anybody got any thoughts?
Any help is greatly appreciated!
This is the makefile I use (simple makefile, that I pretty much found online) :
Code:
VERILOGEX = .v # Verilog file
# testbench path TESTBENCH is passed from the command line
TESTBENCHPATH = testbenches/${TESTBENCH}$(VERILOGEX)
SOURCEPATH = src
#iverilog CONFIG
VERILOG_CMD = iverilog
#VERILOG_FLAGS =
# VVP (iverilog runtime engine)
VVP_CMD = vvp -llogfile -v
#VVP_FLAGS =
#Simulation Vars
SIMDIR = simulation
DUMPTYPE = vcd
#Viewer
WAVEFORM_VIEWER = gtkwave # Waveform viewer executable
all: compile run view
file_check:
ifeq ($(strip $(FILES)),)
@echo "FILES not set. Use FILES=value to set it. Put mutltiple files in quotes"
@exit 2
endif
testbench_check:
ifeq ($(strip $(TESTBENCH)),)
@echo "TESTBENCH not set. Use TESTBENCH=value to set it."
@exit 2
endif
check: file_check
$(VERILOG_CMD) -t null $(FILES)
# Setup up project directory
new :
echo "Setting up project ${PROJECT}"
mkdir src testbench simulation
compile : testbench_check
mkdir -p simulation
$(VERILOG_CMD) -o $(SIMDIR)/$(TESTBENCH) $(TESTBENCHPATH) $(SOURCEPATH)/*
run : testbench_check
$(VVP_CMD) $(SIMDIR)/$(TESTBENCH) -$(DUMPTYPE) $(VVP_FLAGS)
mv dump.$(DUMPTYPE) $(SIMDIR)/$(TESTBENCH).$(DUMPTYPE)
view : testbench_check
$(WAVEFORM_VIEWER) $(SIMDIR)/$(TESTBENCH).$(DUMPTYPE)
clean : testbench_check
rm $(SIMDIR)/$(TESTBENCH)*The basic use is:
make all TESTBENCH=testbench.v
I have simulated many minor design with this setup, without any problems. However when simulating my last design, which is a bit larger (containing around 20 modules) the simulation gets a bit problematic.
Initially, the simulation finished without any problems. But as the testbench passes a certain amount of clock cycles, the simulation never finishes. No error message appears, and it does not crash, it just never finishes. The last message to be printed is this:
VCD info: dumpfile dump.vcd opened for output.
I tried simulating the exact same files in Active HDL (student edition, Windows), and it worked fine. It didn't take more than a second or two either, so the runtime is not the problem it seems.
I have tried letting iVerilog run for quite some time too without any luck. I could of course just switch to Active HDL and Windows, but that would be a last resort, as I already have a good setup going in Ubuntu with IVerilog and gtkwave.
I tried using diiferent output formats, such as lx2 etc. as well but it didn't help.
Anybody got any thoughts?
Any help is greatly appreciated!