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about vhdl code to be written in xilinx

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sadhika_inti

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how to define a component in package? please give the syntax for package for component!!!! i have got an error in the package body for jk flip flop in the line underlined below:
Code VHDL - [expand]
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package body strucpkg is
 
entity jkflp is---- i got parse error with this line
 
port(j,k,clk,set,clr:in std_logic;
                   q: buffer std_logic);
end jkflp;
 
architecture jk of jkflp is
 
begin
 
process(clk,set,clr)
begin
if(clr='0') then q<= '0';
elsif (set='0') then q<='1';
elsif falling_edge(clk) then q<= (not(j) and not(k) and q) or (j and not(k)) or (j and k and not(q));
end if;
end process;
end jk;
 
end jk;                      
                         
 
end strucpkg;
 
Last edited by a moderator:

Why do you write "end jk" twice ?
 

sadhika_inti said:
how to define a component in package? please give the syntax for package for component!!!!
Click to expand...

The general syntax would be


Code VHDL - [expand]

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library ieee;use ieee.std_logic_1164.all;package pkg_entity jkflp -- package name is arbitrary, does not need to be 'pkg_' prefix component jkflp (port(j,k,clk,set,clr:in std_logic; q: buffer std_logic); -- Looks exactly the same as the entity, but simply change 'entity' to 'component'end package pkg_entity jkflp;package body package pkg_entity jkflp isend package body package pkg_entity jkflp; library ieee; -- Note: You need to include the library and packages here alsouse ieee.std_logic_1164.all;entity jkflp (port(j,k,clk,set,clr:in std_logic; q: buffer std_logic);...



Lastly, component declarations are generally not needed at all. You can directly instantiate an entity with the following syntax:

Code VHDL - [expand]

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dut : entity work.jkflp port map(...); -- Direct entity instantiationdut2 : jkflp port map(...); -- Use this if you use a component declaration


Note that the two are almost identical in usage. To create a component declaration, you have to copy/paste the entity declaration (changing 'entity' to 'component') inside a package and then 'use' the package (i.e. use work.pkg_entity jkflp.all). More work, and error prone. The errors come up when you change the entity generics or signals in some fashion because then you need to remember to update the component declaration. Avoid using components, directly instantiate the entity instead.

Kevin Jennings

---------- Post added at 12:08 ---------- Previous post was at 12:03 ----------

Sorry about the 'compressed into garbage' format of the posted code. This web site seems to do this to code at times. Nobody wants to fix it even though there are warnings that one is expected to use the correct code syntax codes...even though that code syntaxer will garble the code up on you.

Kevin Jennings
 
Agree with #3. You should avoid using components, especially if you are a beginner. Use the above mentioned method to instantiate. Its way simpler.

Also, you do not necessarily need to use packages if you are only connecting a few blocks in your design. Simply instantiating the sub-blocks within the main block is sufficient.
 
Last edited:

sorry sir.. it was my mistake in typing.. even after correcting it... i got error with the 'entity' i wrote there... i am not able to know what the error about it is.
 

VHDL does not allow you to declare entities in packages. You can declare components, subprograms, functions, procedures, signals in a package.
 

if entity is not allowed, then how can we define a procedure for a component(declared as component in package) in package body?
 

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