Why functions\procedures in VHDL does not support sequential clock based arguments?

xtcx said:

Hi, I've been having this doubt for a long time, but just thought of asking out. I've been using functions\procedures so far only for combo circuits such as complex adder\mult, muxer, etc. However I've always wondered why not use clock based seq logics, by passing in the arguments, but compiler throws error, so left it. (Sorry, if this is given in any text books, I never read much books fully in that case :-D

1) Why edge functions cannot be used inside function\procedure body?.
2) Is it VHDL limitations?, then how about verilog?
3) Is it not a good to be practiced?.
4) Can it atleast be used for simulation purpose?.

Please share your thoughts to clarify my doubt

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K-J said:

You're correct that functions cannot be procedural (i.e. have any form of 'wait' statements). You're not correct when you lump procedures into that group, they most certainly can.

Functions and procedures accomplish different things:
- Functions return only one thing; procedures can output as many things as you'd like
- Functions cannot 'wait'; procedures can
- The parameters to a function are always inputs; parameters for a procedure can be in/out/inout as you see fit.
- Functions and procedures can be freely used either as part of a standalone concurrent statement or within a process.

Since your doubts seem to be based on some incorrect expectations, perhaps it would be better for you to post some code that you think demonstrate the issue that you see for others to comment.

Kevin Jennings

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procedure dff( D : in std_logic;
                    Q : out std_logic;
                     C : in std_logic);
is
begin
if rising_edge(c) then
Q <= D;
end if;
end procedure;

use xxx.work.all -- pack incl

entity dff_t is

port ( clock : in std_logic;
Q_op : out std_logic);
end diff_t;

archi.....

begin
process (clock)
begin

dff('1',Q_op,clock);
dff('0',Q_op,clock);

end process;

xtcx said:

Thanks a lot buddy....will use this approach from now on....for all sequential logics.

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