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IIR filter design for FPGA

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arash rezaee

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Hi every one. I used FDATOOL to generate chebyshev 2 IIR filter with sampling rate of 95KHz and clock frequency of 12.160MHz. I want to pass frequency from 0 to 15 KHz and stop it at 18KHz. From magnitude response of FDATOOL every thing is fine and it pass up to 15KHz with 0dB when attenuate for higher frequency. I generate HDL code with help of matlab and then use it in my project. But when the input is from 1Hz to 9KHz every thing is fine but above 9KHz it is not stable. why? Another question is, Is it better to design IIR filter ot FIR filter for audio processing?
Regards
Arash
 

95 kHz sampling rate sounds reasonable. What do you mean exactly with "but above 9KHz it is not stable"? Strictly spoken, FIR filters are stable by nature. Did you verify the filter operation in Matlab with the numeric resolution used in the FPGA implementation?

If you are implementing a Chebyshev filter of moderate order, IIR may result in less effort, but generally both should work.
 

Agreed 'above 9khz is not stable' is not a good description and is confusing. Please show data.

Is it better to design IIR filter ot FIR filter for audio processing?
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From a fidelity standpoint, that is a much debated topic and there's lots of info out there.

From an engineering standpoint, that depends on your design requirements/specifications.
 

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