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priority encoder using adder

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manojkhandelwal

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hi
can any one please explain me how to implement an encoder using adder...so that i can use the carry logic in the fpga
will be better if the corresponding verilog code is also provided

thanks i advance

---------- Post added at 18:25 ---------- Previous post was at 18:24 ----------

oh its a priority encoder.....
 

yeah i read it
it gives an easy method to obtain the one hot value for the leading ones......
for example: 1110011 the one hot output will be 0001000 .but i dont need that
i need a binary value which is 0011........
an encoder which converts one hot to binary will do it.....BUT i need an optimal implementation for getting the binary encoded value .....
is there any way like for one hot , to implement it?
Iam referring this in context of implementing it on fpga .....

---------- Post added at 00:34 ---------- Previous post was at 00:32 ----------

Iam really waiting for your reply......
Thanks in advance...
 

Priority mask and priority encoder are closely related in my opinion.

The straightforward method would be to write a behavioral description and check the synthesis results. Research for better implementations if you're not satisfied with the performance or LE count.

You apparently didn't check the mentioned Altera Advanced Synthesis Cookbook, which explicitely covers priority encoders as well.

When a binary encoded output is desired from prioritized request lines, there are two reasonable methods. For smaller input counts, the best implementation is the case statement. A small C program is the best way to build these. The example file implements a 6-input priority encoder in exactly 3 LUTs using the case method.

For larger input sizes, the case statement method becomes infeasible. A reasonable alternative is to implement a bitscan function as described above followed by a one-hot to binary conversion array. An appropriate OR gate array is discussed in Chapter 4, Translation and Format Conversion, in “One-Hot to Binary” on page 4–25. An additional gate is required to deal with the all-lines-0 case.

www.altera.com/literature/manual/stx_cookbook.pdf
https://www.altera.com/literature/manual/cookbook.zip
 

well thanks for the reply
ok i will try with this one.....and figure out if its optimal
Will ask if i have any further doubt ..

thanks again!!
 

You didn't clarify, if an "optimal" implementation is actually required in your application and which criteria (speed or area) are most important. In the linked thread, I tried to make the synthesis tool implement the priority mask logic with minimal LE count, using carry chain.

It turned out, that at least Altera Quartus isn't prepared to utilize the carry chain for non-artithmetical problems. The tool isn't able to find the existing (and rather obvious) optimal implementation (1 LE/per bit using carry chain) by itself. You need to code it with low level primitives to enforce it.

Coding the problem as an arithmetic one enables the carry chain but consumes two instead of one logic elements per bit. It would be interesting to know, if other synthesis tools have similar weaknesses.
 

The criteria is timing , not area (iam using virtex architecture)
anyways if i use carry chain....and as the input is of higher width (say 256) then this implementation will have a lot of delay.......256 carry chains
iam not worried with the no. of LUTs or LEs iam using (as far as its not too high)

---------- Post added at 12:38 ---------- Previous post was at 12:35 ----------

ok i will once again make my question clear
iam implementing a leading one detector..
i need binary and one hot encoded (both) values as output
the implementation should have optimal timing (imp)

---------- Post added at 12:41 ---------- Previous post was at 12:38 ----------

implementing one hot value using adder (add by 1) will clearly degrade timing for long inputs
using a general priority encoder and decoder for the outputs is also not good for such input lengths
will be gr8 if u got any idea ?
 

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