Looking for VHDL library that defines the (+) operator

(+) Operator

anybody knows any VHDL library that defines the (+) operator so as it can add 2 n-bit std_logic_vectors to get both SUM and carry simply represented in (n+1)-bit std_logic_vector ?

Re: (+) Operator

the lib is [ IEEE.NUMERIC_STD ]

If you have FPG@dv search for file : numeric_unsigned.vhd

The function description :

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

package NUMERIC_UNSIGNED is

function "+" (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: UNSIGNED add of two STD_LOGIC_VECTOR vectors that may be of different lengths.

function "+" (L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a STD_LOGIC_VECTOR
-- R which is assumed to be UNSIGNED.

function "+" (L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds a STD_LOGIC_VECTOR vector assumed UNSIGNED, L, to an INTEGER, R.

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Re: (+) Operator

omara007 said:

anybody knows any VHDL library that defines the (+) operator so as it can add 2 n-bit std_logic_vectors to get both SUM and carry simply represented in (n+1)-bit std_logic_vector ?

Click to expand...

Any + operator in any library (std_logic_arith, numeric_std, ...) is able to generate carry.

As my predecessor said, you should use ieee.numeric_std and no other library. numeric_std is the only IEEE official library for math. All the others are compiled into "library ieee;" but are not official IEEE standards. See

As for generating the carry, just use a "n+1" + "n+1" = "n+1" addition by extending the desired length.

Re: (+) Operator

thnx vomit ..
but what king of extension does this (extend) support ? .. and if there are more than implementation to this extension ( there could be zero or sign extension ) ..
and how can this affect the addition process being signed or unsigned ? .. should i mention the SIGNED/UNSIGNED word before the operator ? or declare a package for that ?

Re: (+) Operator

i think..

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

or

use ieee.std_logic_singed.all;

this will do that... the only thing u ahve to do is if ur vectors are of 2 bits... then define resultant of 3 bits.

Re: (+) Operator

No Jey ..
this is not true .. if u used signed or unsigned packages, u won't be able to have a vector of 3-bits as a resultant of 2 input vectors each is 2-bits ..

the right solution is the one that was proposed recently .. in which we extend the inputs .. but we need to know the implementation of the word EXTEND .. is it zero extension or sign extension .. anyhow we can manually extend the inputs ..

Re: (+) Operator

i think it shoudl work....
i m not very much sure... i dont have any vlsi application package rite now with me...
but it should work.... using
a,b :in std_logic_vector( 1 downto 0 );
c : out std_logic_vector( 2 downto 0 ):

process
variable x : std_logic_vector(2 downto 0 )
begin

x := a +b;
c <= x;

this will work sure.. try this..

Re: (+) Operator

Hi friends,
Here is one more method to achieve the target:
Include ieee.std_logic_unsigned.all
==========
use ieee.std_logic_unsigned.all;
==========
write code as follows:
==========
c := ('0' & a) + ('0' & b);
==========
where a and b are n bit vectors and c is n+1 bit vector.

Regards,
Jitendra

Re: (+) Operator

jay_ec_engg said:

process
variable x : std_logic_vector(2 downto 0 )
begin

x := a +b;
c <= x;

Click to expand...

hey Jay
why did u use the intermediate variable x ? why didn't u directly map the result of the addition process to the output port c ?

Re: (+) Operator

then it will show error...
its not synthesizable i think.. i m not sure... but problem willbe there.. thats sure...
have u tried

c<= a + b; ???

Re: (+) Operator

no .. it won't work .. becasue the implementation of the + operator implies that the 2 operands and the result are all of the same vector length ..