How can I implement the up/down gray counter by VHDL?

How can I implement the up/down gray counter by VHDL ?
except binary counter to gray counnter

gray counter

See this (in Verilog, you can convert to VHDL with X-HDL):
**broken link removed**

You can use State Machine approach if counter width is small

vhdl gray counter

Verilog file from:
**broken link removed**

***
`timescale 1ns/100ps
module gray_updown (clk, aclr, ena, up, gray_code);
parameter SIZE = 22;
input clk, aclr, ena, up;
output [SIZE-1:0] gray_code;
reg [SIZE-1:0] gray_code,tog;
integer i,j,k;
always @(posedge clk or negedge aclr)
if (aclr==1'b0) begin
gray_code <= 0;
end
else begin //sequential update
if (ena==1'b1) begin //enabled
tog = 0;
for (i=0; i<=SIZE-1; i=i+1) begin //i loop
//
// Toggle bit if number of bits set in [SIZE-1:i] is even
// XNOR current bit up to MSB bit for Count Up, and
// XOR for Count Down
//
for (j=i; j<=SIZE-1; j=j+1) tog = tog ^ gray_code[j];
if (up==1'b1) tog = !tog;
//
// Disable tog if a lower bit is toggling
//
for (k=0; k<=i-1; k=k+1) tog = tog && !tog[k];
end //i loop
//
//Toggle MSB if no lower bits set (covers code wrap case)
//
if (tog[SIZE-2:0]==0) tog[SIZE-1] = 1;
//
//Apply the toggle mask
//
gray_code <= gray_code ^ tog;
end //enabled
end //sequential update
endmodule
***

Transleted to VHDL with library adding and SIZE = 4

***
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

ENTITY gray_updown IS
GENERIC (
SIZE : integer := 4);
PORT (
clk : IN std_logic;
aclr : IN std_logic;
ena : IN std_logic;
up : IN std_logic;
gray_code : OUT std_logic_vector(SIZE - 1 DOWNTO 0));
END ENTITY gray_updown;

ARCHITECTURE translated OF gray_updown IS


SIGNAL tog : std_logic_vector(SIZE - 1 DOWNTO 0);
SIGNAL i : integer;
SIGNAL j : integer;
SIGNAL k : integer;
SIGNAL gray_code_xhdl1 : std_logic_vector(SIZE - 1 DOWNTO 0);

BEGIN
gray_code <= gray_code_xhdl1;

PROCESS (clk, aclr)
VARIABLE tog_xhdl2 : std_logic_vector(SIZE - 1 DOWNTO 0);
BEGIN
IF (aclr = '0') THEN
gray_code_xhdl1 <= (OTHERS => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (ena = '1') THEN
tog_xhdl2 := (OTHERS => '0');
FOR i IN 0 TO SIZE - 1 LOOP
FOR j IN i TO SIZE - 1 LOOP
tog_xhdl2(i) := tog_xhdl2(i) XOR gray_code_xhdl1(j);
END LOOP;
IF (up = '1') THEN
tog_xhdl2(i) := NOT tog_xhdl2(i);
END IF;
FOR k IN 0 TO i - 1 LOOP
tog_xhdl2(i) := tog_xhdl2(i) AND NOT tog_xhdl2(k);
END LOOP;
END LOOP;
IF (tog_xhdl2(SIZE - 2 DOWNTO 0) = "000000000000000000000") THEN
tog_xhdl2(SIZE - 1) := '1';
END IF;
gray_code_xhdl1 <= gray_code_xhdl1 XOR tog_xhdl2;
END IF;
END IF;
tog <= tog_xhdl2;
END PROCESS;

END ARCHITECTURE translated;
***

VHDL -> EDIF (Synplify Pro) -> Compiling, Fitting, Simulate (MAX+PLUS II )

Fclk = 158 MHz (EPM3032ALC44-4)

It`s really work 8)

up down counter vhdl

VHDL File
----------
Ref : **broken link removed**

-- ############################################################################
-- # Project : Leonardo CBT-Kernel #
-- # #
-- # Filename : counters.vhd #
-- # #
-- # Component : gudNlr : N-bit gray up/down counter #
-- # with synchronous load and asynchronous reset #
-- # #
-- # Model : rtl #
-- # #
-- # Designer : S. Theoharis,N. Zervas #
-- # Institute : VLSI Design Lab., University of Patras #
-- # Date : 01.05.1999 #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ALL;
use work.useful_functions.ALL;

-- gudNlr Entity Description
entity gudNlr is
generic(N: INTEGER := 8);
port(
DIN: in unsigned(N-1 downto 0);
DOUT: out unsigned(N-1 downto 0);
CLK,DOWN,LOAD,R,UP: in std_ulogic;
COUT: out std_ulogic
);
end gudNlr;

-- gudNlr Architecture Description
architecture rtl of gudNlr is
signal istate : unsigned(N-1 downto 0);
signal count : unsigned(N downto 0);
signal load_value : unsigned(N-1 downto 0);
signal binary_out : unsigned(N downto 0);
begin
-- Convert input to binary representation
Grey2Bin(DIN,load_value);
count <= ('0' & istate) + "01" when ((UP = '1') and (DOWN = '0')) else
('0' & istate) - "01" when ((DOWN = '1') and (UP = '0')) else
('0' & istate);

Count_Process: process(CLK,R)
begin
if (R = '1') then
-- reset event
istate <= (OTHERS => '0');
elsif (CLK'event and (CLK = '1') and (CLK'last_value = '0')) then
if (LOAD = '1') then
-- clocked load event
istate <= load_value;
elsif (UP = '1') or (DOWN = '1') then
-- clocked count up/down event
istate <= count(N-1 downto 0);
end if;
end if;
end process Count_Process;

-- Convert input to binary representation
Bin2Grey(istate,binary_out);

-- Assign output values
DOUT <= binary_out(N-1 downto 0);
COUT <= '0' when (DOWN = '0' and UP = '0')
else '1' when (DOWN = '1' and UP = '1')
else not count(N) when (DOWN = '1' and UP = '0')
else count(N);
end rtl;

gray code counter vhdl

Hello,

I study on FERI (**broken link removed**) electronic univirsity.

I must build a counter with PAL, which will count in Gray code from 0 to 9. Counter must have two inputes, load the numbers (input LOAD) and "start" or "ON" (input EN). When the counter goes in not allowed state (9 to 15), the counter must reset.

I using a program ABEL and I simulate the program with data *.jed...

I found this: https://www.asic-world.com/examples/verilog/gray.html but his don't work in my program...

I made a normal counter, but I don't know how to build it in Gray code. My program:

MODULE CNT
title 'stevec gor/dol'
D3..D0,URA,rst,cnten,ld,u_d pin;
D=[D3,D2,D1,D0];
Q3..Q0 pin istype'reg';

Q=[Q3,Q2,Q1,Q0];
X=.X.;
MODE=[cnten,ld,u_d,rst];
LOAD=(MODE==[X,1,X,X]);
HOLD=(MODE==[0,0,X,0]);
UP=(MODE==[1,0,1,0]);
DOWN=(MODE==[1,0,0,0]);
RESET=(MODE==[X,0,X,1]);
equations
Q.clk=URA;
WHEN (LOAD) THEN {WHEN (D>9) THEN Q:=9 ELSE Q:=D;}
ELSE WHEN (HOLD) THEN Q:=Q;
ELSE WHEN (UP) THEN {WHEN (Q==9) THEN Q:=0;
ELSE Q:=(Q+1);}
ELSE WHEN (DOWN) THEN{ WHEN (Q==0) THEN Q:=9;
ELSE Q:=(Q-1);}
ELSE WHEN (RESET) THEN Q:=0;

TEST_VECTORS
([u_d,rst,ld,cnten,URA,D3,D2
,D1,D0] -> [Q3,Q2,Q1,Q0])
[X,0,1,X,.c.,0,1,1,1] -> [0,1,1,1];//NALOŽI 7
[1,0,0,1,.c.,X,X,X,X] -> [1,0,0,0];//ŠTEJ GOR 7NA 8
[1,0,0,1,.c.,X,X,X,X] -> [1,0,0,1];//ŠTEJ GOR 8NA 9
[1,0,0,1,.c.,X,X,X,X] -> [0,0,0,0];//ŠTEJ GOR 9NA 0
[1,0,0,1,.c.,X,X,X,X] -> [0,0,0,1];//ŠTEJ GOR 0NA 1
[X,1,0,X,.c.,X,X,X,X] -> [0,0,0,0];//RESET
[X,0,1,X,.c.,1,1,1,1] -> [1,0,0,1];//NALOŽI 15 IN SPREMENI V 9
[X,0,1,X,.c.,0,1,1,0] -> [0,1,1,0];//NALOŽI 6
[0,0,0,1,.c.,X,X,X,X] -> [0,1,0,1];//ŠTEJ DOL IZ 6 NA 5
[X,0,1,X,.c.,0,0,0,0] -> [0,0,0,0];//NALOŽI 0
[0,0,0,1,.c.,X,X,X,X] -> [1,0,0,1];//ŠTEJ DOL IZ 0 NA 9
[X,0,0,0,.c.,X,X,X,X] -> [1,0,0,1];//HOLD
END

*stevec gor/dol = counter up/down
*ŠTEJ GOR 7 na 8 = count up from 7 to 8
*ŠTEJ DOL IZ 6 na 5 = count down from 6 to 5

I just need counter in Gray and only for counting up... Thank you for your help!

Simon

gray code counter verilog

There is no VHDL code here - but it will give you the principle.
part I:
https://asicdigitaldesign.wordpress.com/2007/05/10/counting-in-gray/

Part II:
https://asicdigitaldesign.wordpress.com/2007/05/13/counting-in-gray-part-ii-observations/

Part III:
https://asicdigitaldesign.wordpress...in-gray-part-iii-putting-everything-together/

hope this helps:

ND.
https://asicdigitaldesign.wordpress.com/