Need Help in Verilog Coding

Hi Experts,

I have a doubt in Verilog Coding. I recently heard that when we convert a spec into a Verilog code we have to capture the timing parameters given in spec(for signal assertions and deassertions) as it is in the code. What does it mean and how to do it?

Thanks in Advance.

hi,
I think you are talking about converting the spec in to Verilog model.

Capturing timing constraints means, making sure that input signals are asserted and deasserted according to timing described in spec.
If you see any sepc, there is always a timing diagram for operation supported.
In case of synchronous operation, timing specified will be setup and hold time requirements of the input signals.
In case of Asynchronous operation, timing specified will be delay timing between two control signals before some other signal which is acting as strobe or control signal for that operation.

In case of Verilog, if you are writing the model for the design then it can be monitored using a Verilog Construct named "Specify".

Hope this answers you question.

GCK

Thanks i will go through the specify construct.