VHDL Test Bench : How To Create A Test Bench Clock of 1KHz

I have one other question regarding the test bench. If I declared that I was going to use a 1KHz clock how do I calculate what my clk_period should be as shown below to achieve a 1KHz clock? By default ISE tool creates a test bench with 1us. Also, when they say clock period I am assuming that are referring to the full clock cycle and not have the clock cycle. Is that true?

I really appreciate everyones help. Thanks!

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-- Clock period definitions
constant clk_period : time := 1 us;
-- Clock process definitions
clk_process rocess
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
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you use a calculator.
1/(F MHz) = clock period in microseconds.

FYI, the code you show is a 1Mhz clock, not 1 KHz.

The period of a frequency is 1/frequency
The frequency of a period is 1/period

The frequency of 1 us (0.000001 sec) period is 1/0.000001sec =1000000=1MHz

For 1KHz you need a period of 1/1000Hz = 0.001 sec = 1ms

Also check this about the period definition

Alex