erece
Junior Member level 3
I am designing cmos logic xor gate and 2:1 multiplexer.
In my design i am using 8 pmos and 8 nmos for 2:1 mux and 6 pmos and 6 nmos for xor gate.
I am using pmos and nmos to implement complement A, means that i am not using complement directly into the circuit.
So , i want to know that is it the minimum no. of transistors used in implementing the above two circuits.
I made the design from the knowledge that pull up network conducts when logic is 1 and pull down nwtwork conducts when logic is 0. please tell if i am wrong.
In my design i am using 8 pmos and 8 nmos for 2:1 mux and 6 pmos and 6 nmos for xor gate.
I am using pmos and nmos to implement complement A, means that i am not using complement directly into the circuit.
So , i want to know that is it the minimum no. of transistors used in implementing the above two circuits.
I made the design from the knowledge that pull up network conducts when logic is 1 and pull down nwtwork conducts when logic is 0. please tell if i am wrong.
