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Reload Design in Modelsim (Xilinx ISE + ModelSim)

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ravics

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1. Is there a way to reload the VHDL design in Modelsim without going back to ISE by using scripting commands in modelsim?

2. What is the procedure to compile UNISIM & Xilinx Corelib in Modelsim?


I got this note from one of the university tutorials : Restarting and running the simulation again will not incorporate any changes you have made to your module or test fixture. To see the effects of these changes, close ModelSim and run the Simulate Behavioral Model process again in ISE.

Any way out? I tried compiling the design .fdo & did restart -f but no changes were incorporated.
 

vcom/vlog are the modelsim commands to recompile some source code.
restart will restart a simulation, with any recompiled code brought in.

If you recompile a library, you will have to recompile all of the files that use that library.
 

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