Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

24-Bit Data Register with Clock Enable and Synchronous

Status
Not open for further replies.
M

maia31

Member level 1
Joined
Jul 10, 2011
Messages
38
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
earth
Activity points
1,519
hi everyone
well i need 24-Bit Data Register with Clock Enable and Synchronous
schematic or vhdl
can you help me?
what should i do?
-------------------------------------------------------------------------
first
i hate ise12.1:grin:
second
because it only has 16bit and under Instances
:sad:
 

Re: 24-Bit Data Register

process (Bus2IP_Clk )
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if en = '1' then
reg(0 to 23) <= reg(1 to 23) & input_data_bit;
end if;
end if;
end process ;
reg(1 to 23) so it is possible to allocate 23 of the 24-bit

---------- Post added at 14:05 ---------- Previous post was at 14:01 ----------

[/COLOR]question is incorrect. What in your understanding of the register. I drew a shift register

---------- Post added at 14:07 ---------- Previous post was at 14:05 ----------

process (Bus2IP_Clk )
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if en = '1' then
reg_out(0 to 23) <= reg_in(0 to 23);
end if;
end if;
end process ;

Register fixation values
 
Last edited:
  • Like
Reactions: maia31

    M

    maia31

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top