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[SOLVED] Modelsim simulation error in VHDL testbench

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soloktanjung

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Hello friends,

I am compiling a VHDL testbench below and got the following modelsim error:

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

signal TDI_TMS		: bit_vector(1 downto 0);

for m in 0 to 14 loop
     TDI_TMS <= ('1', '0') after (1201 + 3000*m); -- line 170
end loop


Code: 
# ** Error: tb_top1.vhd(170): Type error resolving infix expression "+" as type std.standard.time.

I tried many things such as declare a signal using time type but still unable to fix it.
Can anyone give suggestions on how to fix this error or how the other ?

Thanks in advance.

Hairo
 

you need to suggest whether its ps, ns, ms or whatever:

TDI_TMS <= ('1', '0') after (1201 + 3000*m) ns; -- line 170
 

Hello TrickyDicky,

Thanks for your reply.

I did as you suggest (in fact I tried it before) but it gives new error:


Code: 
 TDI_TMS <= ('1', '0') after (1201 + 3000*m) ns; -- line 170

Code: 
# ** Error: tb_top1.vhd(170): Type error resolving infix expression "+" as type std.standard.time.
# ** Error: tb_top1.vhd(170): near "ns": expecting ';'

Thanks.
 

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