How could I get LUT-level netlist in Xilinx ISE?

Hi, I need to convert the high level design to LUT level netlist, and then make corrections to it.

In a paper, author says:

"The translate step generates a Verilog netlist that can easily be parsed. This netlist consists out of declarations of primitive modules of the device"

The netlist is shown as following:

******************************************
...
defparam LUT_37.INIT = 16'hC800;
//synthesis attribute HU_SET of LUT_37 is "SLICE_37";
//synthesis attribute rloc of LUT_37 is "X0Y0";
X_LUT4 LUT37 (.ADR0(n7), .ADR1(n4), .ADR2(n3), .ADR3(n, .o(n41);
....

******************************************
I searched all the files in the project folder, but didn't find this kind of netlist.

I just want to know how to get this kind of netlist in Xilinx FPGA?

Thanks very much!!

If you are using ISE GUI, you have "Generate Post-Synthesis Simulation Model" under "Synthesis-XST".

If you are using Unix, You have netgen tool available along with ISE software.

Command would be : netgen -ofmt verilog X.ngc (This will generate X.v)