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[help]what's the problem with my verilog program?

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bigrice911

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range must be bounded by constant expressions.

I made a program but when it prompts errors when compile.
Range must be bounded by constant expressions

Code: 
function [8*`w-1:0] cast;
input	[`w-1:0] 	data_i;
input	[2:0] 	addr_i;

integer	index; 
for(index=0; index<8; index=index+1)
	if(addr_i == index)
		cast[`w*index+7: `w*index] = data_i; //Range must be bounded by constant expressions	
    else
		cast[`w*index+7: `w*index] = 'bZ; 

endfunction

faint! most verilog compilers do not support this statement!
can anybody give me some hints? thanks!
 

range must be bounded by constant expressions

[...]
u can try other ways
use shift
cast = data_i << addr_i * 'w;
:it cant asign 'bZ

or use mem
reg [`w-1:0] cast [2:0]
for () cast[index] = `w'bz;
cast[addr_i] = data_i;
:it not fit function
 

verilog range bounds are not constants

Verilog Assignment Rule:
part select must constant,
but bit select no limit in procedure assign:
so can use another method,
for(ii = 0;ii<8;ii=ii+1)
if (ii == addr_i)
for(jj = 0;jj<`w;jj=jj+1)
cast[ii*`w+jj] = data_i[jj];
else
for(jj = 0;jj<`w;jj=jj+1)
cast[ii*`w+jj] = 1'bz;
 

xigu, thank you so much!
your answer made me understood my error and your solution DOSE work!
 

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