[SOLVED] WARNING:Xst:1293 FF/Latch <my_flop> is constant in block <my_block>"

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SPI is
  port(clk,  ALOAD : in std_logic;
        D   : in std_logic_vector(11 downto 0);
        SO  : out std_logic;
		  clock_out : OUT STD_LOGIC;
		  chip_select : OUT STD_LOGIC);
end SPI;
architecture archi of SPI is

  signal SPI_signal: std_logic_vector(31 downto 0) := (others => '0'); 
  signal data1 : std_logic_vector (11 downto 0):= (others => '0');
  signal clock : std_logic ;
  
  begin 
 
 process (clk, ALOAD, data1,SPI_signal,D)
 
		variable chip : std_logic;
   begin

-- Shift registers implements the SPI communication
    if (ALOAD='0') then
	
	 --Disable DAC 
	 
		chip :='0'; 
		chip_select <= chip;
		 data1<=D;
	 --Create the data stream for the ADC on the SPARTAN3E board.
	SPI_signal <= "1010"& data1 & "0000" & "0011" & "10101010";
       
	
		elsif (clk'event and clk='1') then
      SPI_signal <= SPI_signal(30 downto 0) & '0';
      SO <= SPI_signal(31);  
		
		--Enable DAC for the data conversion
		
		chip :='1'; 
		chip_select <= chip;
		
    end if;

 end process;
 
 --Clock output for the DAC
 
	clock<=clk;
clock_out <= clock;

end archi;