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piece of verilog code to be translated to vhdl

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neocool

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How would you translate this piece of code from Verilog to VHDL:

reg slck_en;
reg [4:0] count32, count1x;
.
.
.
slck_en <= (count1x == 5'b10010);

===============
The following translation does not pass syntax check:
slck_en <= to_bit(count1x = "10010");
assuming slck_en is of type bit and count1x is std_logic_vector(4 downto 0);


Thanks
neocool
 

neocool said:
How would you translate this piece of code from Verilog to VHDL:

===============
The following translation does not pass syntax check:
slck_en <= to_bit(count1x = "10010");
assuming slck_en is of type bit and count1x is std_logic_vector(4 downto 0);


Thanks
neocool
Click to expand...

count1x = "10010"

produces a type boolean (true/false), whereas to_bit converts from std_logic to bit.

Try

Code: 
slck_en <= '1' when count1x = "10010" else '0';

instead.
 

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