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What's job is the verification job?

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AlexWan

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hi,all

I am confused about this question. Build the Testbench; Write the Test patterns; Compare the function between RTL and gated-netlist/palced-netlist?

Any ohter jobs is verifcation?

Best regards
 

Use Formal Verification & HVL tool..
write test scripts ..
download bin file to fpga and test (sometimes)

Browsing net (hehe.. just kiddin)
 

Thanks

which kind of job is Synthesis? In front-end, how many jobs are there?
 

Usually Fornt end designers a do only basic initial synthesis of the RTL Just to ensure that the code is fully synthesable and working..... Big companies have another group of people who write synthesis constraints and actually sysnthesise and do STA before handing the netlist to physical design team...

You may call them front end designers or backend designers .... I guess there is no clear line of seperation...
 

Verification is a more complicate simulation, it must provide more coverage that the normal simulation. Such as code linde coverage, state transfer coverage and some corner case coverage. And the mostly used verification language is Vera and Specman E language. Now System Verilog have also some functions for verifation.
I think FPGA prototyping is another verification platform, but it's not the verification task.
 

whizkid said:
Usually Fornt end designers a do only basic initial synthesis of the RTL Just to ensure that the code is fully synthesable and working...
Click to expand...

Verification also do the functional compare between the RTL and gate-level netlist or placed netlist. And the pre-simualtion and post-simulation. So verification designer is also back-end design? :eek:

Usually the STA is for Verification ?
 

AlexWan said:
Verification also do the functional compare between the RTL and gate-level netlist or placed netlist. And the pre-simualtion and post-simulation. So verification designer is also back-end design? :eek:
Click to expand...

If you look at the job postings on monster.com for ASIC verification engineer, you will find out that verification usually means functional verification.
LVS (logic versus schematic) or formal verification (RTL vs. netlist) is usually part of the backend process.
Pre-simulation/post-simulation are commonly used in FPGA world. In ASIC, the counterparts are rtl sim and gate sim.
For complex design, verification is 70% of the total effort. It takes a lot of time to write a good testbench with all the verification components (in specman jargon eVC), develop numerous test cases and execute the test cases. It's a tough job.
 

rx300 said:
It takes a lot of time to write a good testbench with all the verification components (in specman jargon eVC), develop numerous test cases and execute the test cases. It's a tough job.
Click to expand...

rx300, thanks

Build the good behavior models, Write detail patterns and Set the atuomatic test environment with shell or perl, Simulation.

I started to study verification just now. Someone tell me that the verification tends to system-level in IP or SOC design. So I am confused in my position.

Are they right? Why to say this is system level?
 

AlexWan said:
I started to study verification just now. Someone tell me that the verification tends to system-level in IP or SOC design. So I am confused in my position.
Click to expand...

For complex SoC, the person developing the verification environment must have some system-level knowledge. For example, E1 framer. If the verification engineer doesn't know AIS and doens't know what the correct response from the framer, then he won't be able to build the right test benches. However, system-level knowledge can always be learned and accumulated. There must be at least one guy on the project who is the "guru" and who knows the system level issues. Otherwise the project is doomed.
System-level knowledge is something nice to have, but nobody can know everything.
 

AlexWan said:
hi,all

I am confused about this question. Build the Testbench; Write the Test patterns; Compare the function between RTL and gated-netlist/palced-netlist?

Any ohter jobs is verifcation?

Best regards
Click to expand...

What you said about the job seems TEST job
 

rx300 said:
AlexWan said:
Verification also do the functional compare between the RTL and gate-level netlist or placed netlist. And the pre-simualtion and post-simulation. So verification designer is also back-end design? :eek:
Click to expand...

If you look at the job postings on monster.com for ASIC verification engineer, you will find out that verification usually means functional verification.
LVS (logic versus schematic) or formal verification (RTL vs. netlist) is usually part of the backend process.
Pre-simulation/post-simulation are commonly used in FPGA world. In ASIC, the counterparts are rtl sim and gate sim.
For complex design, verification is 70% of the total effort. It takes a lot of time to write a good testbench with all the verification components (in specman jargon eVC), develop numerous test cases and execute the test cases. It's a tough job.
Click to expand...

Hi , I am sorry , but LVS should be Layout vs. Schematic. :roll: :roll:
 

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