pipeline and concurrent or non pipeline hardware

deal all

how can pipelining hardware operate at a higher frequency than non pipeline?
if i assume "a*b*C*data" as an example implemented with two case .
first we need to 3 multiplier.
in case non pipeline method if i design this operation in single stage and single process like this
PROCESS(Clk,a,b,c,data)
BEGIN
if(rising_edge(Clk)) then
--multiplication is done in a single stage.
result <= a*b*c*data;
end if;
END PROCESS;
so the result will be 3 multiplier cascaded with them and connect to flip flop
so the result will be available at each clock

in second case pipeline: i divide this operation to 3 stage instead of single stage and i put flip flop after each multiplier stage
so the result will be available after 3 clock .


how can flip flops reduces the delay through the combinatorial logic?
is pipeline faster than non pipeline hardware? why?

wait your help
thanks

Sounds like a homework question to me, but Ill bite.

Simply, more pipeline stages reduces the logic delay from register to register. Each logic element (a gate, multiplier, ram etc) will increase the register to register delay, meaning a slower clock speed is required so that the setup and hold times are not violated.