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Possibly to add margin by over constraining the input path.
Or if you know that the input path is on a clock that is synchronous and the same frequency, but have a well-defined phase offset (like from a PLL).
Thanks for the reply Terry. One more clarification what do u mean by "well-defined phase offset" ? Pls explain how can virtual clock help in this case ?
You use a "virtual" clock to define a clock driving an input to your module. If that clock is different from the source clock inside your module, then timing analysis will automatically take that into account.
Now the "virtual" clock may be different due to phase offsets, or it may be different in frequency, or some combination of both.
Well defined just means that you have some constraints on the phase relationship. Like from a PLL databook. Or if you know that the clock tree of the source module, you can usually compute min/max clock insertion delay.
Pavan, Please use the ASIC methodologies forum to post your ASIC related questions. You will get more response there as many people will look at that particular forum only.
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