swapnashah
Newbie level 3
hi all,
how can i make a top module in verilog code?
it means dat two modules are instatiated in top module and i am giving input to a first module and output of dat module should goes into the input of the second module.
the final output should be from the second module.
pls help me out...
thanx in advance.
how can i make a top module in verilog code?
it means dat two modules are instatiated in top module and i am giving input to a first module and output of dat module should goes into the input of the second module.
the final output should be from the second module.
pls help me out...
thanx in advance.