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hi
Open for example Spartan 6 FPGA Clock resources tutorial(UG382) on page 18 and 19, in the table you can see GCLK XX and according BUFIO XX, on page 18 you will see the path of clock signal through these components. Max frequency, i think, limited by max frequency of fpga flip flops, to use gclk pin, i think, you should create ucf : NET "clock" LOC = "GCLKLOCATION".
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