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Pls help. Verilog HDL .

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Hey, i'm new . Could anybody give me some pointers on how to write a code for traffic light controller in verilog HDL .
Give some tips. pls..
Thank you
 

Hey, i'm new . Could anybody give me some pointers on how to write a code for traffic light controller in verilog HDL .
Give some tips. pls..
Thank you
You can Model a traffic light controller using any of the loops like if, case etc ...

simplest one could be coded using case statement
...

---------- Post added at 22:01 ---------- Previous post was at 21:58 ----------



////or state machine approach is another method ...

simple algorithm

if reset///some initialisation

suppose there is four junction with R1,Y1,G1 ...... for junction 1
case 1 ....(previous case is (green @ Junction one) )
then new case is /////

case 2 ( previous case is )

new case is

....default :
///
end case

---------- Post added at 22:07 ---------- Previous post was at 22:01 ----------

.../////////////sample


examine states ()
{

case 1(green @ junction 1 )
next state is green at junction 2 and yellow at junction 3 and red at all other
some delay

case 2(green @junction 2 )
next state is green at junction 3 and yellow at junction 4 red at all other
some delay
case 3(green @junction 3 )
next state is green at junction 4 and yellow at junction 3 red at all other
some delay
case 4 (green @ junction 4 )
next state is green @ junction 1 and yellow at junction 2 red at all other
some delay
}

---------- Post added at 22:09 ---------- Previous post was at 22:07 ----------

here is a good code example for traffic light
**broken link removed**
 
Hey man , u are great. thanks!
i really appreciate it alot. i promise i wont copy =D
 

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