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how to simulate in-rush current in LDO design?

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Hi all:

how to simulate in-rush current in LDO design?

In real environment, I use active loading for sink 1A from LDO's output, the turn on the ENABLE pin, the current probe shows there is a inrush current.

But how to perform that in computer?
I tried several ways to model the loading current, but every one is constant and fixed. If it is constant and fixed, it won't show the "in-rush" phenomenon.

Any good method to do that ??

Thanks.
 

Just probe supply current in simulation. Inrush current is the inrush in input voltage supply. Of course parasite inductance in real environment might make it worse. So it is better to model them in your simulation.
 

Hello,

What simulation program do you use? If you use a SPICE based simulator, the waveform for the current sink you can generate with a "piece wise linear current source".

You can enter time stamps with current values. the program automatically interpolates between the values entered. You can use "piece wise linear voltage source" to generate every switching signal you like (or input voltage start-up waveform).

You need to add a current probe to measure the inrush current during a transient simulation.
 

Hi:
Is there any paper for eliminate LDO in-rush current ?

I want to use this to test which kind of simulation way is suitable.
Thanks.
 

One of technique is fold-back current limiter. That is, current limiter will become lower when output voltage is lower.
 

Hello,

The complexity of a current limiter (maybe combined with shut down / auto restart) depends on the allowed voltage drop, ratio between nominal current and current limit, etc. You may arrive at a point where it is attractive to design the voltage control loop also.

If you have a separate LDO regulator and have to add a series component for current limiting and measurement (for example current sense resistor and large BJT or mosfet), this will add to the overall voltage drop.

With the availability of cheap transistor pairs with reasonable matching ("BCM"-prefix in EU) and high gain low Vce-sat transistors, you may consider your own design.

What is your nominal current, input/output voltage and maximum drop out voltage?
 

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