Solutions for leading one detector

FvM said:

I see the same logic cell amountof 2*nbit - 1 for both methods. And nbit logic cells using low level primitives as reported.

Click to expand...

FvM said:

As I mentioned in my post #11, the leading one detector (priority mask) can be coded as a simple combinational expression. If a FPGA family is able to put the carry part into the logic cell carry chain, than it can be implemented with one logic cell per bit. If the design compiler can't recognize the behavioral description, low level primitives are way to make it implement the option anyway.
In the present case, the adder solution is quite good, speed-wise, so you won't have to dig for low-level alternatives, normally. I only did, because I was disappointed by Quartus not finding the obvious solution.

Click to expand...

ENTITY leadingone IS
PORT(ein : IN bit_vector(7 downto 0); aus : OUT bit_vector(2 downto 0));
END ENTITY leadingone;

entity numberone is
port(ein, carry : IN bit; aus : out bit);
end entity numberone;

architecture name of numberone is
begin
aus <= ein and not carry;
end name;

ARCHITECTURE name OF leadingone IS
component numberone
port(ein, carry : IN bit; aus : out bit);
end component numberone;
signal intercon : bit_vector(7 downto 0);
BEGIN
for i in 0 to 6 generate
numberone port map
(ein(i), intercon(i+1), intercon(i));
end generate numberone;
intercon(7) <= ein(7);

-- These 3 lines need to be done differently:
aus(0) <= intercon(7) or intercon(5) or intercon(3) or intercon(1);-- every other bit, uneven
aus(1) <= intercon(7) or intercon(6) or intercon(3) or intercon(2);-- every other pair
aus(2) <= intercon(7) or intercon(6) or intercon(5) or intercon(4);-- every other quad
END name;

FvM said:

The second question about "tells the position of first 1" (priority encoder) is still pending. There are basically two methods
- based on the output of the leading bit detector, which is already "one hot" encoded.
- based on the input directly
The first solution ends up in a wide or expression for each position bit and one additional for the all zero case, like below:

Code:

FOR J IN 0 TO NBITA-1 LOOP
   FOR I IN 0 TO NBIT-1 LOOP
      tmp_mask(I) := to_unsigned(i,NBITA)(J);
   END LOOP;
   q(J) <= OR_REDUCE(tmp_mask AND dataout);
END LOOP;
zero <= NOT OR_REDUCE(dataout);

A consideration about priority encoder designs can be found in the Arbitration chapter of the Altera Advanced Synthesis Cookbook. It also mentions a priority masking method using an adder similar to Permute's suggestion.
https://www.altera.com/literature/manual/stx_cookbook.pdf

Click to expand...

I just don't know how I can do it without a process, I prefer a structural description using generate.

Click to expand...