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Are this verilog codes synthesizable?

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krishanu007

krishanu007

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1.always @(c1,c2)
begin
a1 <= a2; // triggering variables are totally different
end

2.@(posedge ready) //...no always,actually inside any always block.
///code/////
 

always @(c1,c2)
begin
a1 <= a2;
end
Here is a combinational logic and it will not be triggering any variable. Actually it's just a buffer, but It's not recommended to use such syntax.
Design Compiler generates warning "a2 is being read, but doesn't appear in sensitivity list of the block".


@(posedge ready) //...no always,actually inside any always block.
///code/////

always@(posedge ... - is a trigger. You can't use another trigger inside existing trigger!
 

kornukhin said:
always@(posedge ... - is a trigger. You can't use another trigger inside existing trigger!
Click to expand...

It works as a trigger if I want to do things..
But Is it synthesizable?
can u tell some tools which can directly tell me any codes synthesizablity?
 

I meant that you can't use Flip-flop inside another flip-flop schematically.
If you want to know is this code synthesizable, just use some synthesize tool (like Design Compiler, RTL Compiler, Quartus...).
 
1) always @(c1,c2)
begin
a1 <= a2;
end

It is synthesizable but it will lead to synthesis-simulation mismatch.
Synthesis tool will infer a simple buffer as it ignores the sensitivity list.
But, this type of coding is not recommended at all.

2) @(posedge ready) //...no always,actually inside any always block.
This type of code is generally used in testbench to wait for a particular signal but it is not supported by the synthesis tools.

regards,
Varun
 

1.always @(c1,c2)
begin
a1 <= a2; // triggering variables are totally different
end

This code is synthesisable creating a buffer but is not good way of writing rtl as in some other scenarios it might cause synthesis simulation mismatch

2..@(posedge ready) //...no always,actually inside any always block.
///code/////

code is synthesisable but it will slow down the simulation

Hope it helps
 

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