bazook
Newbie level 5
Hi,
i need to design ADPLL in VHDL as PM demodulator. The best explained i found in Best, R. E. (2003), Phase-locked Loops: Design, Simulation and Applications, McGraw-Hill. It is something like 74HC297. Could you answer me these questions:
1. What kind of signal should be as an input if i receive almost sine wave from ADC, maybe between ADC and input should be some comparator? Because i cant see that samples vector is an input to JK-FF phase detector.
2. What is the result of this circuit. I know that i can use ADPLL as PM demodulator but which signal and how i can use from this circuit? In analog version i understand but here i dont know.
3. Last question now is do you think implementation from above mentioned book could work? There is e.g. Kcounter as a simple circuit but in datasheets of 74HC297 this part is more complicated. The same thing is with IDcounter.
EDIT:
Ive coped with JK flip-flop, Kcounter but i have problem with IDcounter. Below is my code. Could you help me?
Especially I dont know how I could force some state of signal only for one cycle when some other signal tells me when it should be done.
I enclosed pictures to show IDcounter behaviour.
**broken link removed**
**broken link removed**
T flip-flop
i need to design ADPLL in VHDL as PM demodulator. The best explained i found in Best, R. E. (2003), Phase-locked Loops: Design, Simulation and Applications, McGraw-Hill. It is something like 74HC297. Could you answer me these questions:
1. What kind of signal should be as an input if i receive almost sine wave from ADC, maybe between ADC and input should be some comparator? Because i cant see that samples vector is an input to JK-FF phase detector.
2. What is the result of this circuit. I know that i can use ADPLL as PM demodulator but which signal and how i can use from this circuit? In analog version i understand but here i dont know.
3. Last question now is do you think implementation from above mentioned book could work? There is e.g. Kcounter as a simple circuit but in datasheets of 74HC297 this part is more complicated. The same thing is with IDcounter.
EDIT:
Ive coped with JK flip-flop, Kcounter but i have problem with IDcounter. Below is my code. Could you help me?
Especially I dont know how I could force some state of signal only for one cycle when some other signal tells me when it should be done.
I enclosed pictures to show IDcounter behaviour.
**broken link removed**
**broken link removed**
Code:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity IDcounter is
Port ( IDC : in STD_LOGIC;
C : in STD_LOGIC;
B : in STD_LOGIC;
IDOUT : out STD_LOGIC);
end IDcounter;
architecture Behavioral of IDcounter is
component Tff is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
QT : out STD_LOGIC);
end component;
signal RT : std_logic := '0';
signal Tout : std_logic := '0';
begin
process (IDC, C, B)
begin
if (IDC'EVENT and IDC = '1') then
if (C'EVENT and C = '1') then
if (Tout'EVENT and Tout = '0') then
Tout <= '0';
end if;
end if;
if (B'EVENT and B = '1') then
if (Tout'EVENT and Tout = '0') then
Tout <= '1';
end if;
end if;
IDOUT <= (not IDC) and (not Tout);
end if;
end process;
t0: Tff port map (CLK=>IDC, RESET=>RT,QT=>Tout);
end Behavioral;
Code:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Tff is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
QT : out STD_LOGIC);
end Tff;
architecture Behavioral of Tff is
signal qt_loc : std_logic :='0';
begin
process (CLK)
begin
if CLK'event and CLK='1' then
if RESET='1' then
QT <= '0';
else
qt_loc <= not qt_loc;
QT <= qt_loc;
end if;
end if;
end process;
end Behavioral;
Last edited: