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IBM cms9flp ESD LVS issue

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dkace

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I am trying to run an LVS on an rc clamp for supply that I made.

In LVS i get a short between VSS and VDD and an open on VDD(!)

Obviously there is a problem with the set up of the LVS.

Has anyone encountered and solve this problem?

Thanks,

D.
 

"Obviously" is obviously not the word to use here.

Begin with looking at your pin polygons / texts (whatever
you used to declare connectivity). Right place? Right name?
Maybe more than one VDD pin, one of them on top of VSS?
Though that should give you a label-short warning.

Use the probe tool to select what you know to be VSS and
highlight it. Does the net you know to be VDD get picked up
too? If so, real short.

LVS warnings don't always make literal sense, but they are
trying to tell you something. Sometimes it takes a while of
digging, to figure out what.
 

Well, the issue is that the layout is automatically generated!

I checked every connection every dimension, anything that can cause a problem and yet no luck.

I was hoping that this is common and someone can assist me with a work around
 

It has to be either a real connection, a label connection,
or a bogus connect rule. Don't forget substrate / well
ties as possible shorting paths.
 

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