Counter program problem..

I am a beginner in VHDL.
I have designed a Counter form 0 to 9 and displaying it on 7 seg.
For delay i used the simple loop statement from 0 to 50000...
my code is written below..
My problem is when i am trying to compile code it dont found any errors it just keep doing analysis and no compilation is done.. i compiled some simple programms they are working good... i dont know whether it is a problem of code or what...
( I am using quartus 9.2)







library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(
clk,rst : in std_logic;

op: out std_logic_vector (6 downto 0));
end counter;

architecture count of counter is

begin
process(clk,rst)
variable m : std_logic_vector (3 downto 0) :="0000";

constant max: integer:=50000;
variable cot: integer:=00000;
variable flag: std_logic;
begin

while rst /= '0' loop

loop

if (clk'event and clk='1') then
cot:=cot+1;
end if;
exit when cot=max;
end loop;

flag:='1';

if m="1010" then
m:="0000";
elsif flag='1' then
m := m + 1;
end if;
if(m="0000") then
op<="1000000";
elsif(m="0001") then
op<="1111001";
elsif(m="0010") then
op<="0100100";
elsif(m="0011") then
op<="0110000";
elsif(m="0100") then
op<="0011001";
elsif(m="0101") then
op<="0010010";
elsif(m="0110") then
op<="0000010";
elsif(m="0111") then
op<="1111000";
elsif(m="1000") then
op<="0000000";
elsif(m="1001") then
op<="0010000";
else
op<="1111111";
end if;

flag:='0';
end loop;
end process;
end count;

I wiil be great if i get help...
also i didnt understand what there is diffrence in code between testbench modelling and hardware modelling...

i am using J.Bhaskar(VHDL Primer)
any other good book for hardware modelling in VHDL. or VHDL example book?

This has corect synthesis but it is not the way HW works.

Remember, VHDL is not C, it is not working the same way as C does and it is not a sequential language.

In VHDL, all parts of your code run at the same time, and statements like "exit when cot=max; " will make it impossible to synthesize your code.

I would really suggest you read VHDL cookbook:

https://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

Also, the difference between " testbench modelling" and "hardware modelling" is that the second one can be converted to actual electronic, the first one can be treated just like any other programming language (just to put it simple).

If I was you, I would look for some counter examples and study the code, and remember, the purpose of VHDL code is to create a HW that works, Reset on HW is a port on your flip-flops that when asserted sets the output of the FF into a certain pre-defined state (in most cases '0').

Hope this helps.

farhada said:

This has corect synthesis but it is not the way HW works.

Remember, VHDL is not C, it is not working the same way as C does and it is not a sequential language.

In VHDL, all parts of your code run at the same time, and statements like "exit when cot=max; " will make it impossible to synthesize your code.

I would really suggest you read VHDL cookbook:

https://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

Also, the difference between " testbench modelling" and "hardware modelling" is that the second one can be converted to actual electronic, the first one can be treated just like any other programming language (just to put it simple).

If I was you, I would look for some counter examples and study the code, and remember, the purpose of VHDL code is to create a HW that works, Reset on HW is a port on your flip-flops that when asserted sets the output of the FF into a certain pre-defined state (in most cases '0').

Hope this helps.

Click to expand...

Thanx buddy...

I think i should keep my C mind aside n think by VHDL way....
i waited for 28 min to see if the code compiles or not...
it didint and i got error of loop cant be iterated after 10000...

you have a while loop with nothing in it.

in general, you will almost never use a while loop when writing VHDL. for loops will sometimes be used, but are generally rare.

i have very weak knowledge of VHDL, but the thing is, try to simulate your design first and for simulation it is suggested that keep your delay counter at less counts (for e.g. 50 instead of 500000..)

Umair_ali said:

i have very weak knowledge of VHDL, but the thing is, try to simulate your design first and for simulation it is suggested that keep your delay counter at less counts (for e.g. 50 instead of 500000..)

Click to expand...

i tried it... but it is giving the same error... i think i should study vhdl in detail first..

hey buddies i just got it done....

jst check out this post...