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single bit signal clk from fast clk domain to slow clk

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feel_on_on

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single bit signal from fast clk domain to slow clk domain?

as usually, 2 DFFs was connected to receive clock domain ? but it's possible to lost data .

please tell me how to solved the problem .
 

you need to make an acknowledge mechanism between the two domains to garanti the data transmission, or if you know your maximum difference to maintain the data available for the lowest clock, the time requires.
 

It depends on your real condition
Can you increase the pulse width of fast clock domain to let slow clock capture the signal?
Handshake is another choice for signals of fast clock domain that have enough intervals
Or asynchronous FIFO
 

If the fast clock is consistently much faster than the slow clock, about having the slow clock domain produce a handshake signal which toggles every clock, and having the fast clock domain update those signals which feed the slow clock domain whenever it sees that the handshake has changed state? I would think that, provided the fast clock was sufficiently faster than the slow one, the signals from the fast domain could be regarded as having been generated by the slow clock, with an extra delay of up to 3 fast-clock periods, and thus not require any further synchronization on the slow side.
 

i hav used handshaking with 2ff synchronizer in this context and used the acknowledgement to clear the flop asynchronously but encountered a prob with reset which the flop is having i. i want to combine the reset_n an the ack _n and then use it to clear flop asynchronously . while using a comb logic for this i incurred an Error *E: use of comb logic in path of asynchronous reset to the the flip flop.

can any one enlighten over this
 

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