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How to create RPMs in Verilog code?

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Bartart

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VERILOG RPM problem

Hi!

Anyone who is able to help please do so. I am trying to learn verilog and I have problem creatting RPMs in my verilog code. I am trying to rewrite xilinx xapp416 from VHDL to verilog.


Please help,

10x Bart
 

Re: VERILOG RPM problem

I looked at both peices of code and im not sure what you are refering to when you say RPM and where you are having the issue.. Had to reciently convert 20k lines from vhdl to verilog.. so maybe i can help ya out..

jelydonut
 

Re: VERILOG RPM problem

OK!

My question was not so clear, sorry!

In VHDL code you can see that there is a RPM called "blkram_ff" and after a P&R if you look at the result in floorplanner you can see that all FFs and BRAM is called blkram_ff, this is RPM

My problem is that XST using VHDL code recognize the RPM but using Verilog no. I think it is a problem of attribute U_SET but I don't know Verilog as VHDL and I am :( and :? but looking forward to get the :idea:

It seams that we have the same job converting VHDL 2 VERILOG, but I'm at the begining.

10x, bart
 

Re: VERILOG RPM problem

Hmm.. I guess I was lucky in that my conversion didn't have any instantiated technology specific modules. So I actually have not had this situation come up before/yet. Is it synthesizing? The only thing I could think of is that maybe the required library isn't being compiled with the source or posibly the verilog instantiations are not correct. But that goes back to does it atleast synthesize, which im thinking it does. Have you tried using xhdl just to see what it does to the code and if it would have the same issue with that?

I know that probably isn't any help.. but i tried.

jelydonut
 

Re: VERILOG RPM problem

HI jelydonut!

you 're helpful really and I'm pleased to see that elektroda members are so friendly and dedicated to other members problems.

yes the code is synthesizable, in fact it is working OK, the only thing is that RLOC and some others constraints in VERILOG doesn't work properly.

Cos of my genius CTO I will have to find the solution. :?


looking on this case all the people who say that Verilog is better than VHDL please think twice before saying so. Also I don't know why but xilinx & VHDL seams to me a perfect couple. :wink:

bart
 

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