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synthesis and simulation different behavior

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kuntul

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I have written a mips pipelined datapath using verilog and then it does what it's supposed to do on simulation (ISim), however when I run synthesis and put it on my FPGA board it behaves differently. I have a branch instruction which branches when it's not supposed to, however on simulation everything runs seamlessly. What should I do if I encounter such experience?? I am frustrated now as I don't know how to resolve this.... Can this be because of sensitivity list, which causes the FPGA to behave differently? I have a branch forwarding unit, which looks like the following:

Code: 
module BranchForwardingUnit(Clk, IDEXrd, IFIDrs, IFIDrt, IDEXRegWrite, ForwardC, ForwardD );
									
input Clk;
input [4:0] IFIDrs, IFIDrt, IDEXrd; 
input IDEXRegWrite;
output reg [1:0] ForwardC, ForwardD;

initial begin
 ForwardC = 0;
 ForwardD = 0;
end

always @(IDEXrd, IFIDrs, IFIDrt, IDEXRegWrite) begin

 ForwardC = 0;
 ForwardD = 0;

//EX Hazard
if (IDEXRegWrite == 1)
 if (IDEXrd != 0)
	if (IDEXrd == IFIDrs)
		ForwardC = 2'b10;
   else if (IDEXrd == IFIDrt)
		ForwardD = 2'b10;
		
endmodule
 

I am using iSim. I do believe that the branch module I have above is not the problem as I've removed that and still does the same thing
 

It's probably because there's a problem in the synthesis/implementation step. Maybe your constraints are not good enough. To debug this problem, I suggest you do some basic gate sim with timing with the implementation netlist. Consult your simulator user guide for info on this.

- Hung
 

please let me know on how to do this:

basic gate sim with timing with the implementation netlist.
 

I do believe that the branch module I have above is not the problem as I've removed that and still does the same thing
Click to expand...
I wonder what remains from your code, if you remove the "branch module"?

One problem, why the code does only work in functional simulation is most likely the asynchronous signal compare. Simply consider
the fact, that each bit of the input signals changes it state at a different time. So the value is cycling through a lot of intermediate codes.
E.g. when advancing from "0111" to "1000", you can get all possible 4 bit-codes as intermediate values, so the compare may hit on
any value.
 

Okay... finally after a few hours I managed to find the problem. In my code I use '=' instead of a '<=' when assigning registers and therefore when running synthesis the register got all trimmed out and it behaves differently.

Now here's to the main problem, if I need to use '<=' because I want to synthesize the register, then how would I represent this original code to use '<=':


Code: 
always @(negedge Clk) begin
   if (RegWrite) begin
		RF[WriteRegister] = WriteData;
	end
	
		ReadData1 = RF[ReadRegister1];
		ReadData2 = RF[ReadRegister2];
end


If I change the = to <= in the above.. the simulation now breaks down... how can I achieve the same functionality using <=. Basically what I want to do is to have the register written first before it's being read....
 

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