Rules for contact redundancy when drawing the layout using CMOS process

Hi All,

I am drawing the layout using a cmos process.

I am a bit concerned on "contact redundancy ".

It is better to put as many contacts as possible. But is there any minimum number of contacts to place for a connection? what is the rule to follow there ?
say I have a gate connection ? how many via I should put there to connect poly gate to metal one ?

Thanks in advance.

Best Regards,
whlinfei

Re: contact redundancy

Hi whlinfei,

2 contacts (or 2 vias) per signal connection are fine. Starting with the 0.35µm process (≈10 years ago) this was a "recommendation" (re. good yield) from our fab. At 0.18µm and lower process sizes, this has been enforced by DRC rules.

Rgds, erikl

Re: contact redundancy

erikl said:

Hi whlinfei,

2 contacts (or 2 vias) per signal connection are fine. Starting with the 0.35µm process (≈10 years ago) this was a "recommendation" (re. good yield) from our fab. At 0.18µm and lower process sizes, this has been enforced by DRC rules.

Rgds, erikl

Click to expand...

Hi erikl

Thank you fory your reply.
I am using IBM 130nm process. It seems one contact still can pass DRC.
as this is my first fabrication, I took the caution to have at least two contacts for any connections.
is there any diffference between the redundancy requirement for different level of contact ? Via, V1 , V2....
Thank you in advance

contact redundancy

You can jpass the DRC wiht single contact but the yield will be less creating DFM issues...
Vias should be placed as much as possible minimum 2 via is required at each level of interconnect...

Re: contact redundancy

Fab guys state that contacts and Via12 are the most prone to get defective. If only 1 of -say- 10000 contacts fails, this (single) circuit will fail if it was a single contact. It probably wouldn't matter for a university project (you'd probably get still enough functional chips), for an industrial project, however, the yield increase of a few % by doubling contacts and vias can be quite important.

The necessity for contact/via doubling depends very much on the margin around the contact/via. If this margin is 100nm or lower, doubling is rather advised. If - in some cases - there's actually no area for a second contact or via (e.g. in standard cells), it would be advisable to extend the margin around it - this is sometimes possible and helps the same.

Re: contact redundancy

What margin do you mean? MT enclosure? Or MT to via surrounding MT spacing? Or both?

I've a situation that there's no room to add second via beside exiting one unless if you extended metals (via spacing + via enc + mt spacing rules should be met all)..

Although via's next metal line is so close, but the other successive lines are well away from this via. If the metal just next to this via was shifted, there'll be enough room to extend metal around this via and add red via.

Do you've an algorithm that can be used (from DRC point of view) to identify regions where possible metal spacing shift could be done to extend metal around single via and then add red one? Bearing in mind M1/M2 should be considered in the shift if co-related.

Thanks,
-Knack

erikl said:

Fab guys state that contacts and Via12 are the most prone to get defective. If only 1 of -say- 10000 contacts fails, this (single) circuit will fail if it was a single contact. It probably wouldn't matter for a university project (you'd probably get still enough functional chips), for an industrial project, however, the yield increase of a few % by doubling contacts and vias can be quite important.

The necessity for contact/via doubling depends very much on the margin around the contact/via. If this margin is 100nm or lower, doubling is rather advised. If - in some cases - there's actually no area for a second contact or via (e.g. in standard cells), it would be advisable to extend the margin around it - this is sometimes possible and helps the same.

Click to expand...

Re: contact redundancy

knack said:

What margin do you mean? MT enclosure? Or MT to via surrounding MT spacing? Or both?

Click to expand...

MT enclosure. The reason why vias sometimes fail (because of photolithography resp. etching errors) is the small side margin (MT enclosure) of down to 100nm or even less. If there's enough space, one could enlarge the side margin and so avoid a double via. IMHO this even gives a better connection chance than a second via in the same direction, because this second one could suffer the same damage as the first one.
(The second via of a double via should be on an orthogonal part of the 2 metals to be connected, if possible.)

contact redundancy

first, you need to meet the EM requirement. you need to calculate the total current going into that particular gate. then look at design rule document to find the current density of contact. If min 4 (let's say) are needed, you need 4. more = better. if only need one, it is still advisable to put more than 1. from high speed point of view, more via=less resistance=better performance.

Re: contact redundancy

or you may use 1 rectangular via instead of two square vias if your process supports rectangular vias.