folded cascode opamp gain

Hello everybody.I have a very general question...

I am designing a broadband operational amplifier.My first stage consists of the classical folded cascode topology as depicted below.The design kit i use is IBM's cmos9flp (90nm low power).

After lots of simulations and hand calculations i cannot achieve gain better than 30-31dB...Are those values reasonable,i mean is the maximun i can achieve for this combination of topology-design kit or i can go better??

And my question could be more general..How somebody can approximately estimate,before exhaustive simulations and/or hand calculations,that the maximun value for a given specification is " X " under a specific combination of circuit topology and design kit process?

And my second question : Where should i connect the body (B) terminal of the pmos transistors of the input differential pair?At the source (S) of the transistors or at Vdd??

I would appreciate any helpful answer.Thanks in advance.

I forgot to mention that my supply voltage Vdd is 1.2V and Vss=0 (ground).

30 db of gain in a casocded structure is low. According to me you should check your operating point. Check if all transistors are in saturation. Do you control your output common-mode voltage?
The bulk of the input PMOS can be connected either to the source or to VDD. If connected to VDD you'll have higher threshold voltage and depending on your requirements you may not achieve the upper limit of the input common-mode. Also there will be coupling of the supply noise (if it is a concern) to the input of your amplifier. If you connect the bulk to the source, the layout may not be optimal since the input devices need to be in their own nwell.

First i must say thanks for your answer sutapanaki.

All of my transistor are in saturation since i have via cadence spectre simulator that Vds≈Vdsat+100mV for all of them.I also operate them at the moderate inversion (Vgs-Vth≈100mV).My input and output common mode voltages are set to Vdd/2=600mV and i do not use common mode feedback circuit yet...

Hi jimeece13,

You need to provide more details about your design. What's the bias current? How are you loading your opamp? how are you connecting the inputs to run your simulation? (what test bench are you using in general)?

Your first question seems way to general!!! I would say that only experience allows you to guessimate a range of values for a certain parameter given a topology, but I don't think there's a "recipe" for this.

Your second question, just follow what sutapanaki said, I couldn't agree more.

yes, provide the info that diemilio suggested plus the operating point. Then we'll be able to judge better.

I must say a big thanks to both of you guys for taking time to deal with my questions

Well,in the picture below i show you my dc operating point as a result of cadence spectre simulator.I hope that the info you asked for are clear from the image...
The circuits in the circles are my biasing networks for the input diff pair.The ideal dc voltage sources are used to provide the proper gate biasing for the transistors since i have not created a biasing network for my opamp yet.In addition,as i mentioned earlier i have not created yet a cmfb network.All transistor work in moderate inversion region (approximately Vgs-Vth≈100mV) and in saturation [from spectre results : Vds>Vdsat (Vds≈Vdsat+100mV or more than 100mV)].The simulations give 30dB of low freq gain and i have no problem with the unity gain freq and phase margin specs.I also do not use any load cap or res.

I would appreciate your opinion for my problem with the dc gain.

How do you set the output common mode without common-mode feedback? I guess that's were the problem is...

Can you try adding the following components to your circuit as shown in the attachment? This will provide CMFB (I hope I didn't mess-up with the polarities). To extract the common-mode voltage you use vcvs and you feed it back to vccs. Let us know the result. Also indicate the ro (rather gds) of the transistors.
If you run transient analysis with those ideal components, use caution because it may not be stable.
Also avoid biasing the current sources with voltage applied at the gate. Better if you make a current mirror.

I don't think the problem is related to the common mode voltage at the output cause from simulation it can be seen that the DC output voltage for both the positive and negative terminals is at mid-rail. This was probably achieved by adjusting the input DC voltages. What I noticed from your circuit though is that the DC bias currents are quite high so your output impedance is gonna be low low low (specially for a 90 nm process). I don't think that it would be low enough to give you a gain of only 30 dB but it's a good place to start.

What does your hand calculation tells you?? How much gain are you supposed to be getting from theoretical analysis? What's Vtp and Vtn again? what's your estimated lambda value?

diemilio

Yes, I think you could be right. I looked at the 40nm process for a similar biasing conditions and if I use min L= 40nm everywhere I can get from the NMOS cascode ro=6k and from the PMOS cascode ro=10k. Then the gain comes to about 20dB. This is of course very very approximate and pessimistic because 40nm technology should be worse than 90nm in terms of ro and perhaps transistors here are not minimum length, but yes, it is possible that the gain is only 30db or so.
Still, it is good to have some form of common-mode control. If nothing else, it will allow for more care-free adjustment of the sizes and currents in the circuit.

Dear sutapanaki,

I totally agree with the fact that you need CM control for a practical application, there's no way the circuit is gonna work without one. All I'm saying is that for simulation purposes (to get an initial estimate of the gain) you don't really need it cause you have the freedom to play around with ideal voltage sources to adjust the input offset in such a way that your circuit ends up at its expected operating point.

Thanks for the estimations with the 40 nm process, that gives a much better idea of what could bethe problem.

Yes, I totally agree with what you say about the initial estimate. Of course, CMFB is a must. All I was trying to say was that according to me, using a model for the CMFB even at that initial phase could be beneficial because the guy will have to change transistor sizes and currents and it needs effort every time to precisely adjust the gate voltages to match the currents at the outputs. Instead, if a current mirroring is applied in place of the gate voltages and a common-mode control is used, he doesn't have to think about gate voltages and concentrate on the essential stuff.

to diemilio : My bias currents are quite high enough because i need a very high unity gain frequency (above 1G).Another point,is that i am not aware of the load that my application will have so i am just making estimations all the time in order to come as close to the real conditions as i can...I also followed the Allen-Holberg's folded cascode design guide for the bias currents that says that the current through the pmos cascode load should be 1.2-2 times larger than the bias current of the diff input pmos transistor.From my schematic you can see that : 213.5uA/173.6uA≈1.23.
I can't tell you what Vtn,Vtp values are because i do not know where to find them...IBM's design manual does not say something...Any suggestions where to find them??

to sutapanaki : Well,i do not use CMFB because i haven't decided yet if i will put another stage,so i suppose that CMFB will be set for the total output of my opamp,is it right what i say?In any case i will try to put on my circuit what you sent me.How did you measure via cadence the Ro for pmos cascode load and the nmos folded cascode point???I do not use minimum L..my L is about 2.5-3.5 times larger than L minimum in all the transistors.

Last year i had designed a same folded cascode topology in another TSMC design kit with 1.8V supply and Vss=0 and i easily had a gain above 50dB from this stage...that's what makes me feel that somewhere i miss something and in addition all people that deal with this circuit get a very high gain as seen from papers and other stuff from the internet.

My suggestion would be to just put together a testbench for a single transistor and the the Ids vs. Vgs and Ids. vs. Vds curves (for diferent values of Vgs of course) You can extract almost every single parameter from there (well, approximate values of course). If you have Allen and Holberg go to appendix B, there's a very detailed explanation on how to extract MOS parameter values from simulations.

Once you have all paramters (Vt, Kn, Lambda, etc etc etc) you can get an approx number for the gain... I still think that part of the problem is the high current, but I understand your need for higher bandwidth...

One last question... how are you so sure all your transistors are in saturation if you don't know the values for Vtn and Vtp?? how can you know the value of Vdsat without Vtn and Vtp??
From what I see, your PMOS transistors have a Vgs of -370 mV and a Vds of -400 mV; so for them to be in saturation Vtp would have to be larger than -30 mV which seems rather small (small in absolute value). am I missing something here??

Hope this helps,

diemilio

Ok,i will take a look at the Appendix of Allen-Holberg's book and see what i can estimate theoritically...

When saying Vtn,Vtp you mean the threshold voltages of nmos,pmos transistors respectively??These are indicated on the schematic after the simulation within cadence spectre finishes.I have omitted them on the schematic i posted here.The value of the threshold voltage is not constant,for example it depends on the L value i choose for a transistor.Do you mean something else with Vtn,Vtp??

I am pretty sure that all the transistor are in saturation because when the simulation finishes i go to Results-->Print-->DC Operating Point and i check the Vds & Vdsat values for every transistor on my schematic,then for nmos i have Vds>Vdsat (approx. Vds=Vdsat+100mV or more) and for pmos Vds more negative than Vdsat (100mV or more,more negative Vds than Vdsat).I am considering something wrong for saturation of the fets???

ro, or gds should be annotated the same way you annotate gm from the operating point of the transistors. Or you can simulate and extract it. I personally don't use lambda, K and other square law parameters when I work with modern technologies, simply because they are no more constants but change withL, operating point etc.
Of course at the end you control the common-mode at the output of your amplifier. But you can still use a common-mode controll when you design first only the first stage. The outputs of the first stage go to NMOS transistors (or PMOS transistors) as input of the second stage. You can use Vgs of those transistors as a reference for your common mode controll - you won't be too far from reality.
The Ro of the cascoded portions are as usual ≈gmc*ro1*ro2, where gmc is the transconductance of the cascoded transistor, ro1 the output resistance of the cascoded transistor and ro2 - the ro of the transistor below the cascode.

sutapanaki : do you agree with my last post for the assumption i make in order to have my transistor in saturation region??how do you check the saturation for your designs?

and another question...can i use in a design two different types of fets (for example the regular fets and the low threshold voltage fets)?ofcourse,if it is acceptable i will do this always with pairs of transistors so as to avoid mismatches.

Yes, that's the definition of saturation Vds>Vdsat - at least in square law terms. The question is what is Vdsat. To get a feeling of the behavior of the transistors, do a simulation of Id vs. Vds curve, as diemilio suggested. Do it for your operating point i.e. for the Vgs the transistor in the schematic is at. Then see for yourself if the transition from linear to saturation is sharp or gradual. And decide where exactly this transition happens. In general, you can use Vgs-Vth, or Vdsat as a guideline for the region of operation. You can also use 2/gm/Id as it is equal to the over-drive voltage for a square law transistor. I have heard people claiming that even 25mv of margin between Vds and Vdsat is ok, but I always prefer to be on the safe side and leave at least 100mV.
Another useful simulation is to simulate ro (gds) of the transistor for a fixed over-drive voltage and sweeping Vds. See if you get the expected shape of the variation of ro and if you can judge from there where the transistor enters saturation.

I have never worked on 90nm or below... but in general i would check the gm, gm/Id, threshold, vdsat and ro (impedance ) for pmos and nmos for different length.

without knowing absolute threshold voltage (forgetting the variations) i cant say if 1.2V will be enough to stack 4 transistors.

if ur process allows for a low threshold devices, i would go ahead and use them as they will help get some swing at the outputs, if ur are looking for a gain > 60dB you have to do gain boosting.

search for this paper -- u can find it in google -- High Speed, High Gain OTA in a Digital 90nm CMOS Technology , one of the author is Øyvind Berntsen. this should give u some more insight.


Question: for a broadband amplifer shouldnt we use inductors in load, and a chain of Common source before we amplify them fully.

i hope this is useful...