Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

for loop in VHDL with not 1 step size

Status
Not open for further replies.

raghava

Member level 2
Joined
Jul 31, 2008
Messages
51
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Activity points
1,870
for loop in VHDL

HI all,


For loop in VHDL is implemented as follow.

for i in 0 to 10 loop
--body
end loop;

Here, i incremented by 1 every time.

But how should I write the loop when I need i should be incremented by 2 or more.

Expecting your answers
 

for loop in VHDL

maybe you can use like that=>
for i in 0 to 5
2*i -- use like that
end loop
 

for loop in VHDL

what is the purpose because I feel you mostly able to do almost everything without for loop in VHDL if you are designing some RTL or even test case....
 

Re: for loop in VHDL

Try this
for i in 0 to 10 loop
--body
i := i + 1; -- This will increment the loop index by 2
end loop;
--
Amr Ali

Added after 6 minutes:

I am sorry about the previous reply.
The index of the for loop can't be changed inside the loop. You can only read it.
What about using a while loop?
--
Amr Ali
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top