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FIR filter using Distributed Arithmetic

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vampiro

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Im trying to implement an FPGA based FIR filter using Distributed arithmetic. I need to find a structure to implement. hope someone can help me out finding a schematic to implement
thanks [/quote]
 

first design an lut according to your filter cofficent(all possible combination to your bit pattern),then call to your values according to your input which is multiplierless method
 

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