iamxo
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I designed a sample/hold amplifier for 14bit 100Ms/s ADC input. In typical simulation, the sample/hold amplifier shows good performance, which has 95dB SFDR. However, in slow corner(mos slow, cap slow, 120deg temp), the sample/hold amplifier shows bad fft results with 80dB SFDR。
I checked each part of my circuit, and found the opamp is the cause of low SFDR at slow corner. In typical condition, my opamp has closed-loop GBW 900Mhz, but in slow corner, the closed-loop GBW is 745Mhz。So, if i want to design a sample/hold amplifier which has 90dB SFDR in simulation, should I design a circuit that ensures 90dB SFDR at all corners??
btw, i use tsmc .18um process, Does it has so large corner variation, which leads to 15dB difference from tt corner to ss corner..
Anyone gives me some advice to design the sample/hold circuit to ensure good performance.
I checked each part of my circuit, and found the opamp is the cause of low SFDR at slow corner. In typical condition, my opamp has closed-loop GBW 900Mhz, but in slow corner, the closed-loop GBW is 745Mhz。So, if i want to design a sample/hold amplifier which has 90dB SFDR in simulation, should I design a circuit that ensures 90dB SFDR at all corners??
btw, i use tsmc .18um process, Does it has so large corner variation, which leads to 15dB difference from tt corner to ss corner..
Anyone gives me some advice to design the sample/hold circuit to ensure good performance.
