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2.5 Gbps PRBS Generator Schematics?

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rfmw

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prbs generator

have anybody been involved in designing a PRBS generator above 500 Mbps for test and measurement equipment for optical communications?

i want to design a 2.5 Gbps PRBS (2^7-1), but none experience in this field yet...

any schematics, links or tips about this welcome!

regards,
rfmw
 

Re: prbs generator

rfmw said:
have anybody been involved in designing a PRBS generator above 500 Mbps for test and measurement equipment for optical communications?

i want to design a 2.5 Gbps PRBS (2^7-1), but none experience in this field yet...

any schematics, links or tips about this welcome!

regards,
rfmw
Click to expand...



Hi,

I am facing the same problem and have to design a PCB for PRBS Generator. If you have solved your problem please help me. Any schematic or tips ??

Regards
Avii13
 

How do you plan to design a PRBS core, in an IC or using discrete logic chips?
 

Discrete LFSR upto about 3 GHz should work with Onsemi MC100EP logic series. XOR propagation delay 250 ps, FF setup 50 ps.
 
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FvM said:
Discrete LFSR upto about 3 GHz should work with Onsemi MC100EP logic series. XOR propagation delay 250 ps, FF setup 50 ps.
Click to expand...

Yes, I'm using discrete IC's and the same series. In my project I have to provide clock to two 2^7-1 PRBS with single clock source. As a clock driver I'm using insemi's NB100LVEP221. the output of two PRBS are fed to MUX to get a 1.25 Gbps output rate.

For clock I"m using onsemi's NBXSBA024 crystal Oscillator.

Actually I'm new to PCB designing so not able to decide how to proceed.

Pins of IC which are not of use should be left open or should be connected to ground??
I need help to complete the project on time..
 

NC pins can be left open. FR-4 laminate is sufficient for 2.5Gbps. Use as much differential transmission lines as possible. Make a careful (on paper) design of all setup and hold times, and delays for the clock distribution circuit.

Your plan is to mux two 1.25Gbps PRBS' into one 2.5Gbps. Why not using ONSemi's 10Gbps logic and go straight to the full-clock topology (clock=2.5GHz)?

In addition, try to use devices that have termination resistors in the chips. Making termination with 0805/0603 resistors is quite unfortunate, but necessary. Probably 4-layer PCB will be a must.

FvM: what about the FF's prop delay?
 
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what about the FF's prop delay?
Click to expand...
Good point. You see, that I didn't actually implement a design. Propagation delay seems to enforce usage of 10 GHz NB7xx logic series.
 

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