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How to combine Xilinx XST and Synplify codes into one design

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kequal

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A question of a novice

The logic of one FPGA is divided into two parts which are designed by two men respectively. They use different synthesis tools. One uses xilinx XST and the other uses Synplify. When the two parts of code are combined into one design, neither synthesis tools can assure that these two men could get the same results as they did under their own tools.

We want to generate a package or IP core from one man's design, so when combining the code, the other man needn't synthetize it again.
But we don't konw how to do this, or is there any better ideas to solve the problem?
 

Sthg. you can do is working with black boxes. It is to say, you generate a netlist (i.e. with Synplify) of one part of the code and instantiate it as a component in the vhdl code that is going to be synthetised with the other tool( XST in this case).

If you are using ISE as project manager, you add this netlist as another source file, or if you work in another way, perhaps you will need to add an attribute (see xst help).

Anyhow, using any of the flows/synthesis tools, I recommend you to register inputs to this "black box", and outputs from the "black box". If not there will be logic not optimized and it may give you troubles.
 

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