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it's an FPGA but with a flash prom into this chip ... to make the same advantage that a CPLD.
but you don't forget, fpga need time to program himself by a flash
but with such a samml density (about a few thousands of LE I think) it's really quick to get the FPGA flash (I think the biggest one can be programmed by the end of 100 ms) that's why it is called instant boot...
but with such a samml density (about a few thousands of LE I think) it's really quick to get the FPGA flash (I think the biggest one can be programmed by the end of 100 ms) that's why it is called instant boot...
From the process point of view, it is a FPGA. However, it can complete configuration itself before end of Power-on-Reset, so it is same as CPLD in practice.
obviously : it's a FPGA with a configuration flash embedded inside... Thus, it is saw like a CPLD from the outside (short time configuration because of the little matrix, and no need to download bitstream at startup...)
But it IS a FPGA (despite what ALTERA is saying) with Logic Elements and so on...
It is true the MAXII is SRAM based liked FPGA architecture and the number of LE is so small it's configuration time is minimal so it acts just like a CPLD.
Nice thing about this part is that in addition to it's configuration flash there is a very small FLash that can be used to configure I2C SPI and other external devices that require a very small amount of Non-Volatile Configuration Memory (this is usually a EEPROM of some sort). If you can take advantage of this it's like getting an EEPROM for free.
It is and stays a FPGA architecture, with all the pros and cons.
Yes, it's nice, but don't call it a CPLD. Therefore it need to be very strict timing, and this can't be guaranteed in this architecture.
Lattice has a similar device for more than a year now (XPLD). This architecture is clearly a CPLD, configures also in less than 100us, has lots of memory and has some other features like PLLs, LVDS IOs, high performance and is also low cost.
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